Patent US4847522A successfully refreshed from Google Patents.
US4847522A
Expired / Lapsed
US
⏱️ 0.0 years remaining
CMOS amplifier/driver stage with output disable feature
Assignee: Maxim Integrated Products Inc
•
Filing: 1988-06-08
•
Granted: 1989-07-11
•
Expires: 2008-06-08
Abstract
Abstract The invention relates to an output circuit capable of producing an output signal which may be disabled, leaving the output terminal in a high impedance state capable of being driven externally to a voltage significantly outside the bounds of the output circuit power supply. The output circuit of the invention includes two terminals adapted to be connected to a power supply capable of providing a supply voltage. The output circuit includes an MOS transistor having a substrate, source and drain terminals and a gate, one of the source and drain terminals being coupled to one of the power supply terminals. A second transistor has three terminals including a control terminal and two other terminals, one of which is coupled to the other of the source and drain terminals of the MOS transistor, and the other of which is coupled to the other power supply terminal. An output terminal is coupled between the one terminal of the second transistor and the other of the source and drain terminals of the MOS transistor. A means responsive to an external signal is provided for rendering the output terminal in a high impedance state. A substrate control circuit coupled to the substrate, source and drain terminals of the MOS transistor has a means (1) for detecting whether the voltage at the output terminal is within the voltage range of the power supply, and (2) for controlling the voltage on the substrate of the MOS transistor such that neither its source-substrate nor its drain-substrate junctions can become forward biased, while at the same time providing a voltage capable of disabling both the bipolar and the MOS transistors upon receipt of the external signal. This circuit, unlike prior art circuits, allows the output terminal to be driven significantly beyond the limits of the voltages at the terminals of the power supply, thus permitting its use in "wired-or" configurations which are important where line driver outputs are used, allowing operation with multiple power supplies having differing voltages, or with no power supply at all.
Inventors
- 👤 Roger W. Fuller
- 👤 David Bingham
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 16:53
CPC Classifications
H; H03; H03K; H03K17/00; H03K17/51; H03K17/56; H03K17/567; H03K17/10; H03K17/102; H03K17/687; H03K17/6871; H03K17/6874; H03K2217/00; H03K2217/0018
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
261 words
An output circuit capable of producing an output signal which may be disabled, leaving the output terminal in a high impedance state capable of being driven externally to a voltage significantly outside the bounds of the output circuit power supply voltages, comprising: two terminals coupled to a power supply capable of providing supply voltages; a first MOS transistor having a substrate, a source terminal, a drain terminal and gate, one of said source and drain terminals being coupled to one power supply terminal; a second transistor having three terminals including a control terminal and two other terminals, one of said two other terminals being coupled to the other of said source and drain terminals of said first MOS transistor and the other of said two other terminals being coupled to the other power supply terminal; an output terminal coupled to the coupled terminals of said MOS and said second transistor; means responsive to an external signal for rendering said output terminal in a high impedance state; a substrate control circuit coupled to said substrate, source and drain terminals of said first MOS transistor, said substrate control circuit having a means for (1) detecting whether the voltage at said output terminal is within the voltage range of said power supply and (2) for controlling the voltage on said substrate of said first MOS transistor such that neither its source-substrate nor its drain-substrate junctions can become forward biased while at the same time providing a voltage capable of disabling both said second transistor and the MOS transistor upon receipt of said external signal.
Claim 2
Dependent Claim
261 words
An output circuit capable of producing an output signal which may be disabled, leaving the output terminal in a high impedance state capable of being driven externally to a voltage significantly outside the bounds of the output circuit power supply voltages, comprising: two terminals coupled to a power supply capable of providing supply voltages; a first MOS transistor having a substrate, a source terminal, a drain terminal and gate, one of said source and drain terminals being coupled to one power supply terminal; a second transistor having three terminals including a control terminal and two other terminals, one of said two other terminals being coupled to the other of said source and drain terminals of said first MOS transistor and the other of said two other terminals being coupled to the other power supply terminal; an output terminal coupled to the coupled terminals of said MOS and said second transistor; means responsive to an external signal for rendering said output terminal in a high impedance state; a substrate control circuit coupled to said substrate, source and drain terminals of said first MOS transistor, said substrate control circuit having a means for (1) detecting whether the voltage at said output terminal is within the voltage range of said power supply and (2) for controlling the voltage on said substrate of said first MOS transistor such that neither its source-substrate nor its drain-substrate junctions can become forward biased while at the same time providing a voltage capable of disabling both said second transistor and the MOS transistor upon receipt of said external signal.
Claim 3
Dependent Claim
23 words
The output circuit of claim 1 further characterized by said second transistor being bipolar and having a base electrode as its control terminal.
Claim 4
Dependent Claim
24 words
The output circuit of claim 1 further characterized by said second transistor being an MOS transistor having a gate electrode as its control terminal.
Claim 5
Dependent Claim
57 words
The output circuit of claim 1 further characterized by the addition of a gate control circuit coupled to the gate of said first MOS transistor, said gate control circuit connecting the gate of said first MOS transistor to its substrate upon receipt of said external signal, and said disabling voltage being the voltage applied to said substrate.
Claim 6
Dependent Claim
39 words
The output circuit of claim 4 further characterized by the addition of a means for coupling said gate control circuit to the control terminal of said second transistor for disabling said second transistor upon receipt of said external signal.
Claim 7
Dependent Claim
70 words
The output circuit of claim 1 further characterized by said substrate control circuit comprising second and third MOS transistors having their sources coupled together, each having its drain coupled to one of the source and drain terminals of said first MOS transistor, each having its substrate coupled to its source, and each having its gate coupled to the other of said source and drain terminals of said first MOS transistor.
Claim 8
Dependent Claim
257 words
An output circuit capable of producing an output signal which may be disabled, leaving the output terminal in a high impedance state capable of being driven externally to a voltage significantly outside the bounds of the output circuit power supply voltages, comprising: two terminals coupled to a power supply capable of providing supply voltages; a first MOS transistor having a substrate, a source terminal, a drain terminal and gate, one of said source and drain terminals being coupled to one power supply terminal; a bipolar transistor having a base, an emitter and a collector, said emitter being coupled to the other of said source and drain terminals of said first MOS transistor and said collector being coupled to the other power supply terminal; an output terminal coupled between said emitter of said bipolar transistor and said other of said source and drain terminals of said first MOS transistor; means responsive to an external signal for rendering said output terminal in a high impedance state; a substrate control circuit coupled to said substrate, source and drain terminals of said MOS transistor, said substrate control circuit having a means for (1) detecting whether the voltage at said output terminal is within the voltage range of said power supply and (2) for controlling the voltage on said substrate of said first MOS transistor such that neither its source-substrate nor its drain-substrate junctions can become forward biased while at the same time providing a voltage capable of disabling both the bipolar and the MOS transistor upon receipt of said external signal.
Claim 9
Dependent Claim
257 words
An output circuit capable of producing an output signal which may be disabled, leaving the output terminal in a high impedance state capable of being driven externally to a voltage significantly outside the bounds of the output circuit power supply voltages, comprising: two terminals coupled to a power supply capable of providing supply voltages; a first MOS transistor having a substrate, a source terminal, a drain terminal and gate, one of said source and drain terminals being coupled to one power supply terminal; a bipolar transistor having a base, an emitter and a collector, said emitter being coupled to the other of said source and drain terminals of said first MOS transistor and said collector being coupled to the other power supply terminal; an output terminal coupled between said emitter of said bipolar transistor and said other of said source and drain terminals of said first MOS transistor; means responsive to an external signal for rendering said output terminal in a high impedance state; a substrate control circuit coupled to said substrate, source and drain terminals of said MOS transistor, said substrate control circuit having a means for (1) detecting whether the voltage at said output terminal is within the voltage range of said power supply and (2) for controlling the voltage on said substrate of said first MOS transistor such that neither its source-substrate nor its drain-substrate junctions can become forward biased while at the same time providing a voltage capable of disabling both the bipolar and the MOS transistor upon receipt of said external signal.
Claim 10
Dependent Claim
57 words
The output circuit of claim 7 further characterized by the addition of a gate control circuit coupled to the gate of said first MOS transistor, said gate control circuit connecting the gate of said first MOS transistor to its substrate upon receipt of said external signal, and said disabling voltage being the voltage applied to said substrate.
Claim 11
Dependent Claim
38 words
The output circuit of claim 8 further characterized by the addition of a means for coupling said gate control circuit to the base of said bipolar transistor for disabling said bipolar transistor upon receipt of said external signal.
Claim 12
Dependent Claim
70 words
The output circuit of claim 7 further characterized by said substrate control circuit comprising second and third MOS transistors having their sources coupled together, each having its drain coupled to one of the source and drain terminals of said first MOS transistor, each having its substrate coupled to its source, and each having its gate coupled to the other of said source and drain terminals of said first MOS transistor.
Claim 13
Dependent Claim
298 words
An output circuit capable of producing an output signal which may be disabled, leaving the output terminal in a high impedance state capable of being driven externally to a voltage significantly outside the bounds of the output circuit power supply, comprising: two terminals coupled to a power supply capable of providing a supply voltage; a cascode circuit including first and second MOS transistors, each having a substrate, a source terminal, a drain terminal and gate, one of said source and drain terminals of said first MOS transistor being coupled to one power supply terminal and the other of said source and drain terminals of said first MOS transistor being coupled to one of the source and drain terminals of said second MOS transistor; a bipolar transistor having a base, an emitter and a collector, said emitter being coupled to the other of said source and drain terminals of said second MOS transistor and said collector being coupled to the other power supply terminal; an output terminal coupled between said emitter of said bipolar transistor and said other of said source and drain terminals of said second MOS transistor; means responsive to an external signal for rendering said output terminal in a high impedance state; a substrate control circuit coupled to the substrate, source and drain terminals of said second MOS transistor, said substrate control circuit having a means for (1) detecting whether the voltage at said output terminal is within the voltage range of said power supply and (2) for controlling the voltage on said substrate of said second MOS transistor such that neither its source-substrate nor its drain-substrate junctions can become forward biased while at the same time providing a voltage capable of disabling the bipolar and said second MOS transistor upon receipt of said external signal.
Claim 14
Dependent Claim
298 words
An output circuit capable of producing an output signal which may be disabled, leaving the output terminal in a high impedance state capable of being driven externally to a voltage significantly outside the bounds of the output circuit power supply, comprising: two terminals coupled to a power supply capable of providing a supply voltage; a cascode circuit including first and second MOS transistors, each having a substrate, a source terminal, a drain terminal and gate, one of said source and drain terminals of said first MOS transistor being coupled to one power supply terminal and the other of said source and drain terminals of said first MOS transistor being coupled to one of the source and drain terminals of said second MOS transistor; a bipolar transistor having a base, an emitter and a collector, said emitter being coupled to the other of said source and drain terminals of said second MOS transistor and said collector being coupled to the other power supply terminal; an output terminal coupled between said emitter of said bipolar transistor and said other of said source and drain terminals of said second MOS transistor; means responsive to an external signal for rendering said output terminal in a high impedance state; a substrate control circuit coupled to the substrate, source and drain terminals of said second MOS transistor, said substrate control circuit having a means for (1) detecting whether the voltage at said output terminal is within the voltage range of said power supply and (2) for controlling the voltage on said substrate of said second MOS transistor such that neither its source-substrate nor its drain-substrate junctions can become forward biased while at the same time providing a voltage capable of disabling the bipolar and said second MOS transistor upon receipt of said external signal.
Claim 15
Dependent Claim
46 words
The output circuit of claim 11 further characterized by the addition of a gate control circuit coupled to the gate of said first MOS transistor, said gate control circuit connecting the gate of said first MOS transistor to its substrate upon receipt of said external signal.
Claim 16
Dependent Claim
57 words
The output circuit of claim 12 further characterized by the addition of a gate control circuit coupled to the gate of said second MOS transistor, said gate control circuit connecting the gate of said second MOS transistor to its substrate upon receipt of said external signal, and said disabling voltage being the voltage applied to said substrate.
Claim 17
Dependent Claim
38 words
The output circuit of claim 13 further characterized by the addition of a means for coupling said gate control circuit to the base of said bipolar transistor for disabling said bipolar transistor upon receipt of said external signal.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-07-10 | 1993-01-09 | 1993-07-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-07-10 | 1997-01-09 | 1997-07-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-07-10 | 2001-01-09 | 2001-07-11 | $7700.00 | Window Closed / Lapsed |