Carry circuit suitable for a high-speed arithmetic operation

Claim 1

A carry circuit having a first block which produces a first carry signal (C1) according to sum data of a first plurality of bits and carry data of said first plurality of bits which are arithmetically operated therein, and a second block (10) which produces a second carry signal (C2) according to said first carry signal and sum data (S 4 to S 7 ) of a second plurality of bits and carry data (C 4 to C 7 ) of said second plurality of bits which are arithmetically operated therein, said second block comprising: a carry input terminal receiving said first carry signal; a first means (70, 71) provided independently of said carry input terminal for generating a first signal having a fixed first level which corresponds to the one of two levels that said first carry signal takes and a second signal having a fixed second level which corresponds to the other of said two levels independently of said first carry signal; a second means (50, 51, 52, 53, 57, . . , 50", 51", 52", 53", 57") receiving said first signal, said second signal, said sum data of said second plurality of bits and said carry data of said second plurality of bits for producing two output signals independently of said first carry signal before said second block receives said first carry signal, said two output signals having a first level and a second level, respectively, according to said first and second signals when said sum data of said second plurality of bits all have the same one of said first and second levels, a buffer means (62, 63) receiving said two output signals and for providing two buffered output signals, and a third means (60, 61) coupled to said buffer means and said carry input terminal for selecting either one of said two bufferred output signals in accordance with said first carry signal after said second block receives said first carry signal, the selected buffered output signal being outputted from said second block as said second carry signal (C2).