US4845654A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Pseudo random noise code generator
Assignee: Faurecia Clarion Electronics Co Ltd
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Filing: 1988-07-21
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Granted: 1989-07-04
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Expires: 2008-07-21
Abstract
Abstract A pseudo random noise code generator in which a modular type shift register includes a multiplexer selecting the input for every stage thereof and a flipflop, whose input is the output of the multiplexer, the flipflop serving as the highest stage of the modular type shift register and feeding back the output thereof to each of the stages, and it is possible to control the number of stages of said shift register in operation by address-controlling the modular type shift register.
Inventors
- 👤 Masaaki Harada
- 👤 Masahiro Hamatsu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 20:43
CPC Classifications
H; H03; H03K; H03K3/00; H03K3/84; H04; H04L; H04L9/00; H04L9/06; H04L9/065; H04L9/0656; H04L9/0662; H04L2209/00; H04L2209/12
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
141 words
A pseudo random noise code generator comprising: a modular type shift register constructed by connecting a plurality of circuit constructing units in cascade, each unit consisting of an exclusive OR gate, a first flipflop holding temporarily operation results of the exclusive OR gate, an AND gate whose output is connected with an input of the exclusive OR gate and controls operations and a steering gate setting the initial state of the first flipflop; a multiplexer selecting one of the inputs of said flipflops in said circuit constructing units of said modular type shift register; a second flipflop holding temporarily the output of said multiplexer; and means for taking out the output of said second flipflop and at the same time feeding back said output to the AND gate in each of said circuit constructing units of said modular type shift register
Claim 2
Dependent Claim
141 words
A pseudo random noise code generator comprising: a modular type shift register constructed by connecting a plurality of circuit constructing units in cascade, each unit consisting of an exclusive OR gate, a first flipflop holding temporarily operation results of the exclusive OR gate, an AND gate whose output is connected with an input of the exclusive OR gate and controls operations and a steering gate setting the initial state of the first flipflop; a multiplexer selecting one of the inputs of said flipflops in said circuit constructing units of said modular type shift register; a second flipflop holding temporarily the output of said multiplexer; and means for taking out the output of said second flipflop and at the same time feeding back said output to the AND gate in each of said circuit constructing units of said modular type shift register
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-07-03 | 1993-01-02 | 1993-07-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-07-03 | 1997-01-02 | 1997-07-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-07-03 | 2001-01-02 | 2001-07-04 | $7700.00 | Window Closed / Lapsed |