US4845379A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Sense circuit for detecting absence of a pulse train
Assignee: International Business Machines Corp
•
Filing: 1988-07-05
•
Granted: 1989-07-04
•
Expires: 2008-07-05
Abstract
Abstract A low-cost circuit capable of detecting the absence of a pulse train such as the pulse train generated by a fan cooling output circuit of open collector design. The detection circuit is capable of sensing that a pulse output has stopped in either a high or low state by converting the pulse train to a level that can be compared to a reference. The circuit design insures that the steady state voltage level decays to an under voltage value when the pulse train stops regardless of whether the fan output stops in a high or low state.
Inventors
- 👤 Ronald W. Carlsten
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 15:31
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/19; G; G01; G01R; G01R31/00; G01R31/34; G01R31/343
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
167 words
A sensing circuit for detecting the absence of pulses in a pulse train comprising: a first terminal connected to the pulse train source, a first resistor connected between a voltage source terminal and the first terminal; a diode having its anode connected to the voltage source terminal; a capacitor having one terminal connected to said first terminal and another terminal connected to the cathode of the first diode; a second diode having its anode connected to the cathode of the first diode and having its cathode connected to one terminal of a second capacitor; the other terminal of the second capacitor being connected to ground; and third and fourth resistors being connected in series between the cathode of the second diode and ground, and a comparator receiving a first input from the junction point of said second and third resistors and receiving a second input from another reference signal terminal, and an output terminal connected to the output of the comparator for receiving a pulse error signal.
Claim 2
Dependent Claim
167 words
A sensing circuit for detecting the absence of pulses in a pulse train comprising: a first terminal connected to the pulse train source, a first resistor connected between a voltage source terminal and the first terminal; a diode having its anode connected to the voltage source terminal; a capacitor having one terminal connected to said first terminal and another terminal connected to the cathode of the first diode; a second diode having its anode connected to the cathode of the first diode and having its cathode connected to one terminal of a second capacitor; the other terminal of the second capacitor being connected to ground; and third and fourth resistors being connected in series between the cathode of the second diode and ground, and a comparator receiving a first input from the junction point of said second and third resistors and receiving a second input from another reference signal terminal, and an output terminal connected to the output of the comparator for receiving a pulse error signal.
Claim 3
Dependent Claim
119 words
A sensing circuit for detecting the absence of pulses upon the interruption of an alternating pulse train comprising: an input node for receiving the pulse train; voltage conversion means connected to the input node for converting the pulses of the pulse train to a steady state DC signal level higher than the voltage level of the alternating pulses; and comparator means connected to the conversion means for comparing the DC signal level with a reference voltage, the comparator means producing an output when the DC level of the conversion means falls below the reference voltage level as a result of the absence of pulses from the pulse train regardless of the state in which the pulse train is interrupted.
Claim 4
Dependent Claim
119 words
A sensing circuit for detecting the absence of pulses upon the interruption of an alternating pulse train comprising: an input node for receiving the pulse train; voltage conversion means connected to the input node for converting the pulses of the pulse train to a steady state DC signal level higher than the voltage level of the alternating pulses; and comparator means connected to the conversion means for comparing the DC signal level with a reference voltage, the comparator means producing an output when the DC level of the conversion means falls below the reference voltage level as a result of the absence of pulses from the pulse train regardless of the state in which the pulse train is interrupted.
Claim 5
Dependent Claim
47 words
The sensing circuit of claim 2 wherein the conversion means includes first and second unidirectional means connected together, first charging means connected between said input node and the common juncture of the unidirectional means, and second charging means connected to the output of the second unidirectional means.
Claim 6
Dependent Claim
43 words
The sensing circuit of claim 3 further including a voltage divider means connected to the common juncture of the second unidirectional means and the second charging means and having the center of the divider network connected as an input to the comparator means.
Claim 7
Dependent Claim
19 words
The reference sensing circuit of claim 4 wherein said unidirectional means are diodes and said charging means are capacitors.
Claim 8
Dependent Claim
32 words
The sensing circuit of claim 5 wherein a reference terminal is connected to the anode of the first diode and a resistor is connected between the reference terminal and the input node.
Claim 9
Dependent Claim
22 words
The sensing circuit of claim 6 wherein the anode of the second diode is connected to the cathode of the first diode.
References Cited (Backward Citations)
US3258669A
Cited
US2847565A
Cited
US3069558A
Cited
US3068367A
Cited
US3149243A
Cited
US3187202A
Cited
US3305732A
Cited
US3264496A
Cited
US3405234A
Cited
US3403269A
Cited
US3506848A
Cited
US3514685A
Cited
US3522544A
Cited
US3497816A
Cited
US3653018A
Cited
US3940698A
Cited
US3790818A
Cited
US4158148A
Cited
US4322642A
Cited
US4262213A
Cited
US4746820A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-07-03 | 1993-01-02 | 1993-07-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-07-03 | 1997-01-02 | 1997-07-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-07-03 | 2001-01-02 | 2001-07-04 | $7700.00 | Window Closed / Lapsed |