Supply voltage and clock signal monitor

Claim 2

A monitor circuit for sensing the supply voltages and the rate of a clock signal applied to an electronic circuit and for providing a monitor output signal, the state of which indicates the condition of the supply voltages and clock signal, comprising in combination: a reference voltage source; a first differential means for comparing a first supply voltage against said reference voltage and for providing an output when the amplitude of the first supply voltage is at or above a desired operating range as compared against said reference voltage; clock rate means for receiving a clock signal and for converting the rate of said clock signal into a clock condition signal, the amplitude level of which indicates the rate of said clock signal; and a second differential means for receiving a second supply voltage and said reference voltage and for comparing the difference between said second supply voltage and said reference voltage against the difference between said clock condition signal and said first differential means output signal to provide said monitor output signal, which output signal assumes a first state when the difference between all compared voltages and signals is equal to or less than a selected threshold and assumes a second state when the difference between all compared voltages and signals is greater than the slected threshold.

Claim 3

The monitor circuit according to claim 1 wherein said clock rate means is comprised of: a first capacitor means for receiving said clock signal, said capacitor means being charged and discharged by the amplitude transitions of said clock signal; a second capacitor means connected to sense the charge on said first capacitor and for storing a portion of the charge for a period of time greater than one amplitude transition of said clock signal; a diode means connected to said second capacitor means for passing current in one direction when the charge on said second capacitor means is above a selected level corresponding to the rate of said clock signal; and a third capacitor means connected to said diode means for storing the passed current from said diode means as a charge and for providing said condition signal when the stored charge on said third capacitor means reaches the selected level.

Claim 4

The monitor circuit according to claim 2 wherein said third capacitor means is comprised of: a first capacitor connected between said diode means and a reference point; a first resistor connected to said first capacitor; a second resistor for connecting said first resistor to said second supply voltage; and a second diode means connecting the juncture of said first and said second resistors to the corresponding input of said second differential means. 4 The monitor circuit according to claim 1 wherein said first differential means is comprised of: a pair of transistors, each of said transistors, having base, emitter and collector electrodes; A first resistor connecting the emitters of said pair of transistors to said first supply voltage; a second resistor connecting the base of one of said pair of transistors to said first supply voltage; a third resistor connecting the base of said one of said pair of transistors to a common potential point; a fourth resistor connecting the collector of the other of said pair of transistors to said second supply voltage; the base of said other transistor being connected to said reference voltage, the collector of said one transistor connected to a common potential point; and a diode coupler connecting the collector of said other transistor to said second differential means.

Claim 5

A monitor circuit for sensing the supply voltages and the rate of a clock signal applied to an electronic circuit and for providing a monitor output signal the state of which indicates the condition of the supply voltages and clock signal, comprising in combination: a reference voltage signal source; a first differential means for comparing the amplitude of a first supply voltage against the amplitude of said reference voltage signal and providing an output proportional to the difference between said amplitudes; clock rate means for sensing said clock signal and for providing a condition signal of one state when the sensed clock signal has a rate equal to or above a desired rate and for providing a condition signal of a second state when the sensed clock signal has a rate below the desired rate; and a second differential means for comparing the amplitude of a second supply voltage against the amplitude of said reference voltage signal and for comparing the difference between the amplitude of said second supply voltage and the amplitude of said reference voltage against the state of the condition signal and said first differential means output signal to provide said monitor output signal, one state of which indicates that the difference between all compared signals is equal to or less than a selected threshold value and another state of which indicates that the difference between all compared signals is greater than the selected threshold value.

Claim 6

A monitor circuit for sensing the supply voltages and the rate of a clock signal applied to an electronic circuit and for providing a monitor output signal the state of which indicates the condition of the supply voltages and clock signal, comprising in combination: a reference voltage signal source; a first differential means for comparing the amplitude of a first supply voltage against the amplitude of said reference voltage signal and providing an output proportional to the difference between said amplitudes; clock rate means for sensing said clock signal and for providing a condition signal of one state when the sensed clock signal has a rate equal to or above a desired rate and for providing a condition signal of a second state when the sensed clock signal has a rate below the desired rate; and a second differential means for comparing the amplitude of a second supply voltage against the amplitude of said reference voltage signal and for comparing the difference between the amplitude of said second supply voltage and the amplitude of said reference voltage against the state of the condition signal and said first differential means output signal to provide said monitor output signal, one state of which indicates that the difference between all compared signals is equal to or less than a selected threshold value and another state of which indicates that the difference between all compared signals is greater than the selected threshold value.

Claim 7

The monitor circuit according to claim 5 wherein said clock rate means is comprised of: a first capacitor means for receiving said clock signal, said capacitor means being charged and discharged by the amplitude transitions of said clock signal; a second capacitor means connected to sense the charge on said first capacitor and for storing a portion of the charge for a period of time greater than one amplitude transition of said clock signal; a diode means connected to said second capacitor means for passing current in one direction when the charge on said second capacitor means is above a selected level corresponding to the rate of said clock signal; and a third capacitor means connected to said diode means for storing the passed current from said diode means as a charge and for providing said condition signal when the stored charge on said third capacitor means reaches the selected level.

Claim 8

The monitor circuit according to claim 6 wherein said third capacitor means is comprised of: a first capacitor connected between said diode means and a reference point; a first resistor connected to said first capacitor; a second resistor for connecting said first resistor to said second supply voltage; and a second diode means connecting the juncture of said first and said second resistors to the corresponding input of said second differential means.

Claim 9

The monitor circuit according to claim 5 wherein said first differential means is comprised of: a pair of transistors, each of said transistors having base, emitter and collector electrodes; a first resistor connecting the emitters of said pair of transistors to said first supply voltage; a second resistor connecting the base of one of said pair of transistors to said first supply voltage; a third resistor connecTing the base of said one of said pair of transistors to a common potential point; a fourth resistor connecting the collector of the other of said pair of transistors to said second supply voltage; the base of said other transistor being connected to said reference voltage, the collector of said one transistor connected to a common potential point; and a diode coupler connecting the collector of said other transistor to said second differential means.