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US4843392A
Expired / Lapsed
US
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Digital-to-analog converter with digital correction
Assignee: Individual
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Filing: 1988-03-23
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Granted: 1989-06-27
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Expires: 2008-03-23
Abstract
Abstract A true N-bit digital-to-analog converter (DAC), i.e. a DAC the absolute accuracy error of which is less than 1 LSB (or ±1/2 LSB), can be composed of easy obtainable and low-priced components. The DAC distinguishes a very fast, highly accurate, high resolution conversion of a digital input code into an equivalent voltage or current. Two or more DACs are cascaded in order to attain a high resolution. Only one ROM and an associated DAC are necessary to obtain an accuracy error of less than 1 LSB, in consequence of the increased resolution. The final trimming can be conducted in packaged form of the device through the ROM programming. For example, a true 16-bit DAC can be composed of three equal true 8-bit DACs, wherein their absolute accuracy error must be less than 0.992 LSB. A ROM with the storage capacity of only 256 bytes is necessary.
Inventors
- 👤 Zdzislaw Gulczynski
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 04:28
CPC Classifications
H; H03; H03M; H03M1/00; H03M1/06; H03M1/0617; H03M1/0675; H03M1/66
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
145 words
Digital-to-analog converter having output, for converting digital input code, having most and least significant bits, into analog output signal, comprising: a first digital-to-analog converter means coupled to the output of the digital-to-analog converter for converting the most significant bits into a first current; a programmable memory means for converting the most significant bits into a digital correction code; a second digital-to-analog converter means having an output, for converting the digital correction code into a second current; a third digital-to-analog converter means coupled to the output of the second digital-to-analog converter means for converting the least significant bits into a third current, wherein the first, second and third currents have essentially equal weights; a source means for providing a fourth current; and a resistive means for coupling the output of the second digital-to-analog converter means and the source means to the output of the digital-to-analog converter.
Claim 2
Dependent Claim
145 words
Digital-to-analog converter having output, for converting digital input code, having most and least significant bits, into analog output signal, comprising: a first digital-to-analog converter means coupled to the output of the digital-to-analog converter for converting the most significant bits into a first current; a programmable memory means for converting the most significant bits into a digital correction code; a second digital-to-analog converter means having an output, for converting the digital correction code into a second current; a third digital-to-analog converter means coupled to the output of the second digital-to-analog converter means for converting the least significant bits into a third current, wherein the first, second and third currents have essentially equal weights; a source means for providing a fourth current; and a resistive means for coupling the output of the second digital-to-analog converter means and the source means to the output of the digital-to-analog converter.
Claim 3
Dependent Claim
66 words
Digital-to-analog converter of claim 1 wherein absolute accuracy errors of each the first, second and third digital-to-analog converter means are less than one least significant bit of the respective codes applied thereto, and further wherein the programmable memory means is programmed in such a manner that the absolute accuracy error of the digital-to-analog converter is less than one least significant bit of the digital input code.
Claim 4
Dependent Claim
25 words
Digital-to-analog converter of claim 1 wherein the digital input code has L least significant bits, and further wherein the digital correction code has L bits.
Claim 5
Dependent Claim
58 words
Digital-to-analog converter of claim 1 wherein the digital input code has K most significant bits, further wherein the resistive means includes a node coupled to the output of the second digital-to-analog converter means and a fifth current is flowing to the node, and still further wherein the fifth current is divided by 2 K in the resistive means.
Claim 6
Dependent Claim
17 words
Digital-to-analog converter of claim 1 wherein the first, second and third currents are equally polarized and unidirectional.
Claim 7
Dependent Claim
20 words
Digital-to-analog converter of claim 1 wherein the source means includes a voltage source and a resistor coupled in series therewith.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-06-26 | 1992-12-26 | 1993-06-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-06-26 | 1996-12-26 | 1997-06-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-06-26 | 2000-12-26 | 2001-06-27 | $7700.00 | Window Closed / Lapsed |