US4841500A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Printed circuit board fabrication technique
Assignee: AT&T Inc
•
Filing: 1988-03-17
•
Granted: 1989-06-20
•
Expires: 2008-03-17
Abstract
Abstract The fabrication of a printed circuit board (26) usually includes the step of testing the board with a testing machine (24) to verify operability. The testing machine accomplishes such testing by transmitting test signals to the board via a transmission line (36) and then analyzing each response signals returned from the board in response to the test signals. To reduce the incidence of error, the testing machine (24) is compensated for the propagation delay of the line (12) which is measured by launching a first string of pulses into one end of the line whose opposite end is left open. A second string of pulses is simultaneously launched into a programmable delay line (16) which delays each second pulse by an adjustable interval. After the generation of each first and second pulse, a check is made whether the first pulse has been reflected back to the first end of the transmission line at the same time the second pulse reaches the output of the delay line. If the pulses are not coincident, the delay setting of the delay line is increasaed and then a check is again made whether one of the first and second pulses are coincident. The delay of the delay line is successively increased until the pulses are coincident whereupon the delay of the delay line now equals twice the delay of the transmission line.
Inventors
- 👤 Wha-Joon Lee
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 18:59
CPC Classifications
G; G04; G04D; G04D7/00; G04D7/002; G04D7/003; G01; G01R; G01R31/00; G01R31/28; G01R31/2801; G01R31/2806
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
289 words
A method for fabricating a printed circuit board comprising the steps of: soldering at least one lead of at least one component to a metallized area on an insulative substrate; and testing the circuit board by launching at least one test signal from a testing machine to the circuit board along a circuit path and then analyzing, at the testing machine, each response signal generated by the circuit board and communicated to the testing machine along the circuit path in response to the test signal, each signal incurring a propagation delay over at least a portion of the circuit path traveled thereby, characterized in that: the step of testing further includes the step of compensating the testing machine in accordance with the magnitude of the propagation delays incurred by each signal as it travels along at least a portion of a circuit path, the propagation delays being measured by the steps of: (a) launching a first pulse into a first end of the circuit path so that the first pulse propagates to a node of interest along said path; (b) simultaneously launching a second pulse into one end of a programmable delay line which serves to delay the second pulse from reaching a second end of the delay line by an adjustable time period; (c) checking whether the second pulse has reached the second end of the delay line at substantially the same time the first pulse has reached said node of interest, and, if not, adjusting the delay of the programmable delay line by a predetermined amount; and (d) repeating steps (a)-(c) until the second pulse reaches the second end of the delay line at about the same instant as the first pulse reaches said node of interest.
Claim 2
Independent Claim
289 words
A method for fabricating a printed circuit board comprising the steps of: soldering at least one lead of at least one component to a metallized area on an insulative substrate; and testing the circuit board by launching at least one test signal from a testing machine to the circuit board along a circuit path and then analyzing, at the testing machine, each response signal generated by the circuit board and communicated to the testing machine along the circuit path in response to the test signal, each signal incurring a propagation delay over at least a portion of the circuit path traveled thereby, characterized in that: the step of testing further includes the step of compensating the testing machine in accordance with the magnitude of the propagation delays incurred by each signal as it travels along at least a portion of a circuit path, the propagation delays being measured by the steps of: (a) launching a first pulse into a first end of the circuit path so that the first pulse propagates to a node of interest along said path; (b) simultaneously launching a second pulse into one end of a programmable delay line which serves to delay the second pulse from reaching a second end of the delay line by an adjustable time period; (c) checking whether the second pulse has reached the second end of the delay line at substantially the same time the first pulse has reached said node of interest, and, if not, adjusting the delay of the programmable delay line by a predetermined amount; and (d) repeating steps (a)-(c) until the second pulse reaches the second end of the delay line at about the same instant as the first pulse reaches said node of interest.
Claim 3
Dependent Claim
91 words
The method according to claim 1, characterized in that; (a) the testing machine launches a plurality of test signals into the circuit board via a separate one of a plurality of circuit paths; and (b) the testing machine is compensated for the difference in the propagation delays of the test signals traveling across different circuit paths by the steps of: (1) measuring the propagation delay of each test signal traveling along the corresponding circuit path; and (2) adjusting the propagation delay of each circuit path until all have an equal delay.
Claim 4
Dependent Claim
69 words
The method according to claim 1, characterized in that the testing machine is compensated for any error in phase between the test and response signal by the steps of: (a) measuring the delay incurred by the test signal to travel to the circuit board along the circuit path; and (b) delaying the response signal by an amount at least equal to the measured propagation delay of the test signal.
Claim 5
Dependent Claim
40 words
The method according to claim 1, characterized in that the circuit path has its second end left open so that the first pulse propagates to the second end of said path and is then reflected to the first end thereof.
Claim 6
Dependent Claim
33 words
The method according to claim 1, characterized in that said first pulse is launched into the first end of said circuit path so as to propagate to the opposite end of said path.
References Cited (Backward Citations)
US3896378A
Cited
US4468624A
Cited
US4488297A
Cited
US4516861A
Cited
US4688947A
Cited
US4704036A
Cited
US4736351A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-06-19 | 1992-12-19 | 1993-06-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-06-19 | 1996-12-19 | 1997-06-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-06-19 | 2000-12-19 | 2001-06-20 | $7700.00 | Window Closed / Lapsed |