Method and apparatus for characterizing propagation delays of integrated circuit devices

Claim 3

A method as defined in claim 1 wherein the step of measuring the period between the time said first signal is applied and the time said second signal is applied is carried out by counting clock pulses over a plurality of cycles of said first and second signals, and averaging the results.

Claim 4

A method as defined in claim 1 wherein said channels are connected in series, each one being connected to a preceding one, and the first one connected to said first system input terminal, and said array includes a multiplexer for coupling the output of a selected logic element to said array output terminal.

Claim 5

A method as defined in claim 1 wherein said channels have their input terminals connected to said first system input terminal in common, and said sampler array includes a multiplexer for coupling the output of a selected logic element to said array output terminal.

Claim 6

A method as defined in claim 4 wherein said first and second signals are step-wave signals, and observation of which of said first and second step-wave signals occurs first is made by two-input logic elements, one for each channel receiving a channel delayed first signal and said second signal.

Claim 7

A method as defined in claim 5 wherein said two-input logic element determines during each cycle when both logic signals are low and produces a low output signal until it determines both signals are high to produce a high output signal for positive step-wave first and second signals, and vice versa for negative step-wave first and second signals, and said output signal level from each cycle is stored until the next cycle.

Claim 10

A method as defined in claim 7 wherein at least one additional channel is provided in said array comprised of a conductive metal trace for use in measuring propagation delay through metal traces in integrated circuits, whereby a baseline for propagation delay measurements of channels having active elements is determined by measuring the propagation delay of said additional channel, and having determined said baseline, subtracting said baseline from the measured propagation delay of said plurality of channels before dividing by the number of active elements in said channels to determine the propagation delay of active elements in said channels having different design parameters.

Claim 11

Apparatus for measuring propagation delays of channels in integrated circuits on a semiconductor chip comprising an integrated circuit sampler array on said chip, said sampler array comprising a plurality of two-input logic elements, one logic element for each channel having one input terminal connected to the output of its associated channel and having an output terminal coupled to an array output terminal, a connection from a first system input terminal to an input terminal of said channels, and a connection from a second system input terminal to the second input terminal of each logic element in common, a timing waveform generator off said chip for cyclically producing first and second step-wave signals with controlled delay of said second signal relative to the first signal, means for applying said first signal from said generator to said first system input terminal, means for applying said second signal to said second system input terminal, means comprised of said two-input logic elements for determining which of said first signal propagated through a selected channel and said second signal occurs first during each cycle of said generator, means for increasing the controlled time delay of the second signal if it occurs first, and decreasing the controlled time delay of the second signal if it occurs last during each cycle, and means off of said chip connected to said timing waveform generator for measuring the period between the time said first signal is applied and the time said second signal is applied to said integrated circuit sampler array as a measure of channel propagation time delay.

Claim 12

Apparatus for measuring propagation delays of channels in integrated circuits on a semiconductor chip comprising an integrated circuit sampler array on said chip, said sampler array comprising a plurality of two-input logic elements, one logic element for each channel having one input terminal connected to the output of its associated channel and having an output terminal coupled to an array output terminal, a connection from a first system input terminal to an input terminal of said channels, and a connection from a second system input terminal to the second input terminal of each logic element in common, a timing waveform generator off said chip for cyclically producing first and second step-wave signals with controlled delay of said second signal relative to the first signal, means for applying said first signal from said generator to said first system input terminal, means for applying said second signal to said second system input terminal, means comprised of said two-input logic elements for determining which of said first signal propagated through a selected channel and said second signal occurs first during each cycle of said generator, means for increasing the controlled time delay of the second signal if it occurs first, and decreasing the controlled time delay of the second signal if it occurs last during each cycle, and means off of said chip connected to said timing waveform generator for measuring the period between the time said first signal is applied and the time said second signal is applied to said integrated circuit sampler array as a measure of channel propagation time delay.

Claim 13

Apparatus as defined in claim 9 wherein said channels are connected in series, each one being connected to a preceding one, and the first one connected to said first system input terminal, and said integrated circuit sampler array includes a multiplexer for coupling the output of a selected logic element to said array output terminal.

Claim 14

Apparatus as defined in claim 9 wherein said channels have their input terminals connected to said first system input terminal in common, and said integrated circuit sampler array includes a multiplexer for coupling the output of a selected logic element to said array output terminal.

Claim 15

Apparatus as defined in claim 10 or 11 wherein said two-input logic element includes means for storing its output signal during each cycle until the next cycle, and said waveform generator includes means for reading out the stored signal of a selected two-input logic element at the beginning of each cycle, and storing the signal thus read during the next cycle for control of the increase or decrease of the time delay of said second signal.

Claim 16

Apparatus as defined in claim 12 wherein each two-input logic element is comprised of a two-input Muller C-element.

Claim 17

Apparatus for characterizing propagation delays of active elements in integrated circuits comprising an array of integrated circuit channels on a semiconductor chip, each with a plurality of active elements connected in cascade together with an addressable multiplexer on said chip and a plurality of two-input logic elements on said chip, said active elements in a channel having the same parameters, with active elements in different channels having different parameters, one logic element for each channel on said chip having one input terminal connected to the output of its associated channel and having an output terminal on said chip connected to said multiplexer, whereby selective coupling of said logic elements to said output terminal by said multiplexer is made, a connection from a first system input terminal on said chip to an input terminal on said chip of all channels in common, and a connection from a second system input terminal on said chip to the second input terminal of each logic element in common on said chip, means for cyclically generating first and second step-wave signals with a controlled time delay of said second signal, means for applying said first signal from said generating means to said first system input terminal, means for applying said second signal from said generating means to said second system input terminal, means comprised of said two-input logic elements for determining on chip which of said first signal delayed by propagation through a selected channel and said second signal occurs first during each cycle, means for increasing the controlled time delay of the second signal in said generating means if it occurs first, and decreasing the controlled time delay of the second signal in said generating means if it occurs last during each cycle, means connected directly to said signal generating means for measuring the period between the time said first signal is applied and the time said second signal is applied as a measure of propagation time delay through a plurality of active elements.

Claim 18

Apparatus for characterizing propagation delays of active elements in integrated circuits comprising an array of integrated circuit channels on a semiconductor chip, each with a plurality of active elements connected in cascade together with an addressable multiplexer on said chip and a plurality of two-input logic elements on said chip, said active elements in a channel having the same parameters, with active elements in different channels having different parameters, one logic element for each channel on said chip having one input terminal connected to the output of its associated channel and having an output terminal on said chip connected to said multiplexer, whereby selective coupling of said logic elements to said output terminal by said multiplexer is made, a connection from a first system input terminal on said chip to an input terminal on said chip of all channels in common, and a connection from a second system input terminal on said chip to the second input terminal of each logic element in common on said chip, means for cyclically generating first and second step-wave signals with a controlled time delay of said second signal, means for applying said first signal from said generating means to said first system input terminal, means for applying said second signal from said generating means to said second system input terminal, means comprised of said two-input logic elements for determining on chip which of said first signal delayed by propagation through a selected channel and said second signal occurs first during each cycle, means for increasing the controlled time delay of the second signal in said generating means if it occurs first, and decreasing the controlled time delay of the second signal in said generating means if it occurs last during each cycle, means connected directly to said signal generating means for measuring the period between the time said first signal is applied and the time said second signal is applied as a measure of propagation time delay through a plurality of active elements.

Claim 19

Apparatus as defined in claim 14 wherein at least one additional channel is provided in said array comprised of a conductive metal trace deposited as part of said integrated circuit, whereby a baseline for propagation delay measurements of an integrated circuit may be determined by measuring the propagation delay of said additional channel.