Patent US4841481A successfully refreshed from Google Patents.
US4841481A
Expired / Lapsed
US
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Semiconductor memory device
Assignee: Hitachi Ltd
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Filing: 1988-07-28
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Granted: 1989-06-20
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Expires: 2008-07-28
Abstract
Abstract An SRAM including a memory cell having a high-resistance load element. The load element is formed from a polysilicon film, and an impurity is introduced into a least a part of the polysilicon film for the purpose of increasing the threshold voltage of a parasitic MISFET formed using the load element as its channel region. Alternatively, the deposition of the polysilicon film is carried out at a relatively high temperature, thereby preventing any increase in the current flowing through the load element, and thus reducing the power dissipation in the SRAM.
Inventors
- 👤 Shuji Ikeda
- 👤 Satoshi Meguro
- 👤 Kotaro Nishimura
- 👤 Sho Yamamoto
- 👤 Nobuyoshi Tanimura
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 21:08
CPC Classifications
H; H10; H10D; H10D1/00; H10D1/40; H10D1/47; H10B; H10B10/00; H10B10/15; Y; Y10; Y10S; Y10S257/00; Y10S257/903
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
172 words
A semiconductor memory device having a memory cell including a flip-flop composed of first and second inverters, the output terminals of said first and second inverters being respectively connected to the input terminals of said second and first inverters, each of said first and second inverters being constituted by a MISFET and a load element which is connected in series to said MISFET and which is formed by a polysilicon film, said polysilicon film including a first region of a first conductivity type, a second region of a second conductivity type, and a third region having no impurities of said first and second conductivity types introduced therein and defining said load element, said first region being formed on the side of said polysilicon film which is closer to the end thereof to which a power supply voltage is applied than at least said second and third regions, and said second region being formed on the side of said polysilicon film which is closer to said MISFET than at least said third region.
Claim 2
Dependent Claim
172 words
A semiconductor memory device having a memory cell including a flip-flop composed of first and second inverters, the output terminals of said first and second inverters being respectively connected to the input terminals of said second and first inverters, each of said first and second inverters being constituted by a MISFET and a load element which is connected in series to said MISFET and which is formed by a polysilicon film, said polysilicon film including a first region of a first conductivity type, a second region of a second conductivity type, and a third region having no impurities of said first and second conductivity types introduced therein and defining said load element, said first region being formed on the side of said polysilicon film which is closer to the end thereof to which a power supply voltage is applied than at least said second and third regions, and said second region being formed on the side of said polysilicon film which is closer to said MISFET than at least said third region.
Claim 3
Dependent Claim
36 words
A semiconductor memory device according to claim 1, wherein said first and second conductivity types are respectively n- and p-types, the impurity concentration of said first region being made higher than that of said second region.
Claim 4
Dependent Claim
56 words
A semiconductor memory device according to claim 2, wherein said polysilicon film further includes a fourth region of the first conductivity type, said fourth region being formed on the side of said polysilicon film which is closer to said MISFET than said second region, and having the same impurity concentration as that of said first region.
Claim 5
Dependent Claim
45 words
A semiconductor memory device according to claim 3, wherein said polysilicon film further includes a fifth region of the second conductivity type, said fifth region being formed between said first and third regions and having the same impurity concentration as that of said second region.
Claim 6
Dependent Claim
25 words
A semiconductor memory device according to claim 2, wherein a data line is stacked over at least a part of said second and third regions.
Claim 7
Dependent Claim
28 words
A semiconductor memory device according to claim 5, wherein the gate electrode of said MISFET is formed below at least a part of said second and third regions.
References Cited (Backward Citations)
US4748487A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-06-19 | 1992-12-19 | 1993-06-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-06-19 | 1996-12-19 | 1997-06-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-06-19 | 2000-12-19 | 2001-06-20 | $7700.00 | Window Closed / Lapsed |