High-speed digital multiplier architecture

Claim 2

In an integrated circuit, a mulitiplier architecture comprising: first data input means for inputting a binary X-operand comprising an array of M parallel bits wherein M is an integer greater than or equal to 1; second data input means for inputting a binary Y-operand comprising an array of N parallel bits wherein N is an integer greater than or equal to 1; binary multiplier means for multiplying the X-operand and the Y-operand to produce a binary product comprising an array of M+N parallel bits; means for inputting a load instruction into the multiplier means; load means in the multiplier means responsive to the load instruction for concatenating the X operand and Y operand without multiplying said operands to produce, as said product, a concatenated result in which the M most significant bits are the X operand and the N least significant bits are the Y operand; and output means for outputting the product.

Claim 3

A multiplier architecture according to claim 1 in which the output means is separate from the first and second input means and includes means for outputting the entire product as a parallel array of M+N bits.

Claim 4

A multiplier architecture according to claim 1 in which the output means is separate from the first and second input means and includes means for outputting the product as a pair of time-multiplexed subsets of the product.

Claim 5

A multiplier architecture according to claim 1 in which each array is ordered from most significant to the least significant bit; means including: means for generating the binary multiplier from said operands a series of ordered partial products including a first partial product comprising the least significant bit of the X operand times the Y operand, a last partial product comprising the most significant bit of the X operand times the Y operand, and at least one intermediate partial product comprising a bit between the least and most significant bits of the X operand times the Y operand; means for ordering the partial products in an array in accordance with the significance thereof such that each intermediate and the last partial product is offset by a predetermined number of bits in the direction of the more significant bits from an adjacent partial product of less significance, and the first and last partial products are offset so that the least significant bit of the last partial product is more significant than the most significant bit of the first partial product; and adder means for adding the partial products in accordance with their significance to produce said binary product; the load means including: first means responsive to the load instruction for inputting the Y operand into the first partial product; second means responsive to the load instruction for inputting binary zeroes into the intermediate partial products; and third means responsive to the load instruction for inputting the X operand into the last partial product, so that operation of the adding means concatenates the X operand and the Y operand to form said concatenated result.

Claim 6

A multiplier architecture according to claim 4 in which the third means comprises a multiplexer.

Claim 7

A mulitplier architecture according to claim 1, wherein the binary product is an intermediate Z-product, said multiplier architecture including: means for inputting a format adjust signal to indicate whether the X and Y operands are signed binary fractions; and format adjust means selectively responsive to the format adjust signal for shifting the entire Z-product one bit in a direction of the most significant bit to produce a W-product of 2M parallel bits; the output means being arranged to output the W-product.

Claim 8

A multiplier architecture according to claim 6 including means responsive to said shifting of the Z product to insert a zero bit in the position of the least significant bit in the W product.

Claim 9

A multiplier architecture according to claim 6 including: means for inputting a rounding instruction; means responsive to the rounding instruction for adding a binary one to a selected one of the Mth or (M-1)th significant bit positions of the unshifted Z product; and means selectively responsive to the format adjust signal for selecting the (M-1)th bit when the Z product is to be shifted.

Claim 10

A multiplier architecture according to claim 8 including means for setting a zero status flag when a portion of the W product to be output is equal to zero.

Claim 11

A multiplier architecture according to claim 6 including means responsive to said shifting for detecting a Z product of -1.0×-1.0=+1.0 and setting an overflow status flag.

Claim 12

A multiplier architecture according to claim 1, in which the operands and the products can each include a sign bit, said multiplier architecture including: means for inputting an operand mode instruction to indicate whether each operand is an unsigned or a two's-complement operand; and means responsive to the mode instruction for setting a sign status bit in accordance with a sign bit of the binary product.

Claim 13

A multiplier architecture according to claim 1 in which each of the first and second data input means is a latch controlled by a first clock signal input and the output means is a latch controlled by a second clock signal input, the output latch being responsive to a clock signal transition that is opposite to the clock transition to which the input latch is responsive, so that the first and second clock signal inputs may be paralleled to provide single-clock edge-triggered-like operation.

Claim 14

In an integrated circuit, a multiplier architecture comprising: first data input means for inputting a binary X-operand comprising an array of N parallel bits wherein is an integer greater than or equal to 1; second data input means for inputting a binary Y-operand comprising an array of M parallel bits wherein is an integer greater than or equal to 1; binary multiplier means for multiplying the X-operand and the Y-operand to produce a binary intermediate Z-product comprising an array of N+M parallel bits; each array being ordered from most significant to the least significant bit; format instruction means for inputting a format adjust signal; format adjust means selectively responsive to the format adjust signal for shifting the entire Z-product one bit in the direction of the most significant bit to produce a W-product of N+ M parallel bits; and output means for outputting the W product; whereby the X and Y operands can be signed binary fractions containing a binary point at a predetermined position; and a binary point in the W-product can be aligned with the binary point in one of the X and Y operands.

Claim 15

In an integrated circuit, a multiplier architecture comprising: first data input means for inputting a binary X-operand comprising an array of N parallel bits wherein is an integer greater than or equal to 1; second data input means for inputting a binary Y-operand comprising an array of M parallel bits wherein is an integer greater than or equal to 1; binary multiplier means for multiplying the X-operand and the Y-operand to produce a binary intermediate Z-product comprising an array of N+M parallel bits; each array being ordered from most significant to the least significant bit; format instruction means for inputting a format adjust signal; format adjust means selectively responsive to the format adjust signal for shifting the entire Z-product one bit in the direction of the most significant bit to produce a W-product of N+ M parallel bits; and output means for outputting the W product; whereby the X and Y operands can be signed binary fractions containing a binary point at a predetermined position; and a binary point in the W-product can be aligned with the binary point in one of the X and Y operands.

Claim 16

A multiplier architecture according to claim 13 including means responsive to said shifting of the Z product to insert a zero bit in the position of the least significant bit in the W product.

Claim 17

A multiplier architecture according to claim 13 including means responsive to said shifting for detecting a product of -1.0×-1.0=+1.0 and setting an overflow status flag.

Claim 18

A multiplier architecture according to claim 13 including: means for inputting a rounding instruction; means responsive to the rounding instruction for adding a binary one to a selected one of the Mth or (M-1)th significant bit positions of the unshifted Z product; means selectively responsive to the format adjust signal for selecting the (M-1)th bit when the Z product is to be shifted.

Claim 19

A multiplier architecture according to claim 16 including means for setting a zero status flag when a portion of the W product to be output is equal to zero.

Claim 20

A multiplier architecture according to claim 13, in which the operands and the products can each include a sign bit, said multiplier architecture including: means for inputting an operand mode instruction to indicate whether each operand is an unsigned or a two's-complement operand; and means responsive to the operand mode instruction for setting a signed status bit in accordance with a sign bit of the Z-product.

Claim 21

A multiplier architecture according to claim 13 in which the output means is separate from the first and second input means and is arranged for outputting the entire W-product as a parallel array of N+M bits.

Claim 22

A multiplier architecture according to claim 13, in which the output means is separate from the first and second input means and including a multiplexer for outputting a selected one of the entire W-product of N+M bits and a subset thereof, as a parallel array.

Claim 23

A multiplier architecture according to claim 13 including means for inputting a load instruction and means responsive to the load instruction for concatenating the X operand and Y operand without multiplying said operands to produce, as the Z-product, a result in which the M most significant bits are the X operand and the N least significant bits are the Y operand.

Claim 24

A multiplier architecture according to claim 21, in which the output means is separate from the first and second input means and is arranged for outputting the entire W-product as a parallel array of N+M bits.

Claim 25

A multiplier architecture according to claim 22, in which the output means includes means for outputting a selected one of the entire W-product of N+M bits and a subset thereof, as a parallel array.

Claim 26

A multiplier architecture according to claim 22 in which each of the first and second data input means is a latch controlled by a first clock signal input and the output means is controlled by a second clock signal input, the first clock signal input being inverted relative to the second clock signal input.

Claim 27

In an integrated circuit, a multiplier architecture comprising: first data input latch means for inputting a binary X-operand comprising an array of N parallel bits wherein N is an integer greater than or equal to 1; second data input latch means for inputting a binary Y-operand comprising an array of M parallel bits wherein M is an integer greater than or equal to 1; binary multiplier means for multiplying the X-operand and the Y-operand to produce a binary product comprising an array of N+M parallel bits; an output latch means for outputting the product in the form of said array of N[30 M paralle1 bits; each of said latch means being controlled by a two-polarity enable signal for passing binary data in response to a first polarity and holding binary data in response to a second polarity of the enable signal; first enable signal input means for inputting a first enable signal to the first and second input latch means; and second enable signal input means for inputting a second enable signal to the output latch means so that applying an enable signal of the first polarity to both the first and second enable signal input means enables the operands to pass through the input latch means to be multiplied and enables the product to pass through the output latch means to an output.

Claim 28

In an integrated circuit, a multiplier architecture comprising: first data input latch means for inputting a binary X-operand comprising an array of N parallel bits wherein N is an integer greater than or equal to 1; second data input latch means for inputting a binary Y-operand comprising an array of M parallel bits wherein M is an integer greater than or equal to 1; binary multiplier means for multiplying the X-operand and the Y-operand to produce a binary product comprising an array of N+M parallel bits; an output latch means for outputting the product in the form of said array of N[30 M paralle1 bits; each of said latch means being controlled by a two-polarity enable signal for passing binary data in response to a first polarity and holding binary data in response to a second polarity of the enable signal; first enable signal input means for inputting a first enable signal to the first and second input latch means; and second enable signal input means for inputting a second enable signal to the output latch means so that applying an enable signal of the first polarity to both the first and second enable signal input means enables the operands to pass through the input latch means to be multiplied and enables the product to pass through the output latch means to an output.

Claim 29

A multiplier architecture according to claim 25 including: first clock signal input means for inputting a first clock signal to the first and second input latch means; second clock signal input means for inputting a second clock signal to the output latch means; the first and second clock signal input means being inverted relative to one another so that applying a single clock signal to both clock signal input means causes the operands to be held for multiplication by the multiplier means upon occurrence of a leading edge of the clock signal and the product to be held at the output of the output latch means upon occurrence of a trailing edge of the clock signal.

Claim 30

A multiplier architecture according to claim 26, in which each of said input latch means is a latch, responsive to a first control signal, the first control signal being active when both the first enable signal and first clock signal are active.

Claim 31

A multiplier architecture according to claim 26, in which the output latch means is a latch, responsive to a second control signal, the second control signal being active when both the second enable signal and the second clock signal are active.

Claim 32

A multiplier architecture according to claim 25, wherein the output of the multiplier means is an intermediate Z product, said multiplier architecture including: a format instruction latch means responsive to said first enable signal for inputting a format adjust signal to indicate whether the X and Y operands are signed binary fractions; format adjust means selectively responsive to the format adjust signal for shifting the entire Z-product one bit in a direction of the most significant bit to produce a W-product of N+M parallel bits; and output means for outputting the W product via the output latch means.

Claim 33

A multiplier architecture according to claim 29 including a status flag latch means responsive to said second enable signal for setting status flags; the status flag latch means including overflow flag latch means responsive to the format adjust signal for setting an overflow flag in accordance with the most significant bit of the Z-product.

Claim 34

A multiplier architecture according to claim 25 including an input load instruction latch means responsive to said first enable signal for inputting a load instruction and load means responsive to the load instruction for concatenating the X operand and Y operand without multiplying said operand to produce as said product a result in which the M most significant bits are the X operand and the N least significant bits are the Y operand.

Claim 35

A multiplier architecture according to claim 25, in which the operands and the product can each include a sign bit, said multiplier architecture including: mode latch means responsive to said first enable signal for inputting an operand mode instruction to indicate whether each operand is an unsigned or a two's-complement operand; and sign status latch means responsive to said second enable signal and to the mode instruction for setting a sign status flag in accordance with a sign bit of the product.

Claim 36

A multiplier architecture according to claim 25 including an input round instruction latch means responsive to said first enable signal for inputting a round instruction; round means responsive to the round instruction for rounding the product to an array of N bits; and zero status latch means responsive to said second enable signal and to the round instruction for setting a zero status flag in accordance with the value of the output product.

Claim 37

In an integrated circuit, a multiplier architecture comprising: first clock input means for receiving a first clock signal; first data input means responsive to the first clock signal for receiving and storing a binary X-operand; second data input means responsive to the first clock signal for receiving and storing a binary Y-operand; binary multiplier means for multiplying the X-operand and the Y-operand independently of the frequency of the first clock signal to produce a binary product; second clock input means for receiving a second clock input signal; and output latch means connected to the binary multiplier means to receive the binary product for latching the product in response to the second clock input signal.

Claim 38

In an integrated circuit, a multiplier architecture comprising: first clock input means for receiving a first clock signal; first data input means responsive to the first clock signal for receiving and storing a binary X-operand; second data input means responsive to the first clock signal for receiving and storing a binary Y-operand; binary multiplier means for multiplying the X-operand and the Y-operand independently of the frequency of the first clock signal to produce a binary product; second clock input means for receiving a second clock input signal; and output latch means connected to the binary multiplier means to receive the binary product for latching the product in response to the second clock input signal.

Claim 39

A multiplier architecture according to claim 32 wherein: the first and second input means are responsive to a leading edge of the first clock signal; and the output latch means is responsive to a trailing edge of the second clock signal so that a single clock signal can be provided to both the first and second clock input means for clocking the input means and the output latch means in a master-slave mode.