Apparatus for controlling a switching amplifier

Claim 3

An amplifier output controlling apparatus as set forth in claim 1 wherein said synchronized doubled signal is generated by logically combining said message signal and said first time delayed signal such that a positive going pulse portion of said synchronized doubled signal occurs for each leading and each trailing edge of said message signal.

Claim 4

An amplifier output controlling apparatus as set forth in claim 1 wherein said second delayed signal generating means includes a bit storage element having a first input receptive of said first time delayed signal and a second input receptive of a clock signal, said clock signal being determined as a function of said synchronized doubled signal.

Claim 5

An amplifier output controlling apparatus as set forth in claim 3 wherein said bit storage element generates said second time delayed signal by storing said first time delayed signal until the occurrence of said clock signal which commences following expiration of said preselectable time delay.

Claim 6

An amplifier output controlling apparatus as set forth in claim 4 wherein said preselectable time delay is determined by a first timing means operably initiated by each pulse portion of said synchronized doubled signal, said first timing means being effective for establishing said preselectable time delay as a single value applicable to each half cycle of said message signal.

Claim 7

An amplifier output controlling apparatus as set forth in claim 5 wherein said first timing means includes a first resistor-capacitor timing circuit having a predetermined time constant associated therewith and which is connected to one input of a comparator element, said first timing means also includes a reference voltage circuit connected to a second input of said comparator element and having an adjustable resistor disposed therein which is effective such that upon adjustment, said reference voltage circuit outputs an adjusted reference signal against which said predetermined time constant is compared so as to generate an output of said comparator element which is utilized in developing said clock signal.

Claim 8

An amplifier output controlling apparatus as set forth in claim 6 wherein the output of said comparator element is summed with said synchronized doubled signal so that said clock signal is at least equal to said synchronized doubled signal in duration.

Claim 11

An amplifier output controlling apparatus as set forth in claim 8 wherein said combining means includes a first logic element having a first logic function associated therewith and which is receptive of said disable signal and said first delayed signal, said first logic element producing said first logic signal therefrom, said combining means further including a second logic element having a second logic function associated therewith which results in an output that is opposite in phase to that of said first logic function, said second logic element being receptive of said disable signal and said second delayed signal and being effective for producing said second logic signal therefrom, said second logic signal being 180° out of phase with said first logic signal.

Claim 12

An amplifier output controlling apparatus as set forth in claim 9 wherein said first logic element is an inverting element and said second logic element is a non-inverting element.

Claim 13

An amplifier output controlling apparatus as set forth in claim 9 wherein said overcurrent condition of the power line is sensed by a comparator circuit receptive of a voltage signal at one input, which voltage signal is representative of the amplifier output signal drawn by the power line, said comparator circuit is also receptive of a reference signal at a second input, which reference signal is representative of a threshold level of current in the power line below which said amplifier is operable, said comparator circuit being effective such that, when said voltage signal exceeds said reference signal, said enable signal is converted to said disable signal.

Claim 16

An amplifier output controlling apparatus as set forth in claim 12 further comprising means for measuring a time duration corresponding to said power-up time delay, said time duration commencing from a time when a system operating voltage above a preselected voltage threshold value has been detected and continuing until the expiration of said power-up time delay.

Claim 17

An amplifier output controlling apparatus as set forth in claim 13 further comprising means for supplying said amplifier with an amplifier operating voltage which is substantially higher than said system operating voltage, said voltage supplying means including a plurality of capacitors which are limited as to the amount of voltage that can be developed thereacross until such time as said power-up time delay expires.

Claim 18

An amplifier output controlling apparatus as set forth in claim 13 wherein said enable signal generating means and said time measuring means are effective under conditions additional to a power up condition, said other conditions including a condition where said system operating voltage periodically drops beneath said preselected voltage threshold value.

Claim 19

A switching amplifier and amplifier control apparatus for use on a power line communication system, comprising: means for generating a message signal for transmission over said power line communication system, said message signal containing a plurality of information bits and having a preselected frequency and phase associated therewith, said message generating means further generating a message enabling signal in conjunction with said message signal; means for amplifying said message signal; means for driving said amplified message signal into said power line communication system; logic means in electrical communication with said message signal and being effective upon reception of said message enabing signal, for conditioning said message signal such that under normal operating conditions, said message signal can be communicated to said amplifying means; means for sensing an overcurrent condition at said driving means and generating a current limit signal in response thereto; means for limiting current through said driving means until the expiration of a power up time delay value, such power up time delay value having a duration which is preselected to a value that allows for component settling; means for measuring said power up time delay value and generating a power up time delay signal until said power up time delay value has expired; and means for generating an enable signal and a disable signal, generating said enable signal upon sensing the absence of said current limit signal and the absence of said power up time delay signal, said enable and disable signal generating means further being effective such that, upon sensing at least one of said limit current signal and said power up time delay signal, said enable and disable signal generating means generates said disable signal such that said driving means is prevented from communicating said message signal to said power line communication system.

Claim 20

A switching amplifier and amplifier control apparatus for use on a power line communication system, comprising: means for generating a message signal for transmission over said power line communication system, said message signal containing a plurality of information bits and having a preselected frequency and phase associated therewith, said message generating means further generating a message enabling signal in conjunction with said message signal; means for amplifying said message signal; means for driving said amplified message signal into said power line communication system; logic means in electrical communication with said message signal and being effective upon reception of said message enabing signal, for conditioning said message signal such that under normal operating conditions, said message signal can be communicated to said amplifying means; means for sensing an overcurrent condition at said driving means and generating a current limit signal in response thereto; means for limiting current through said driving means until the expiration of a power up time delay value, such power up time delay value having a duration which is preselected to a value that allows for component settling; means for measuring said power up time delay value and generating a power up time delay signal until said power up time delay value has expired; and means for generating an enable signal and a disable signal, generating said enable signal upon sensing the absence of said current limit signal and the absence of said power up time delay signal, said enable and disable signal generating means further being effective such that, upon sensing at least one of said limit current signal and said power up time delay signal, said enable and disable signal generating means generates said disable signal such that said driving means is prevented from communicating said message signal to said power line communication system.