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US4839895A
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Early failure detection system for multiprocessor system
Assignee: NEC Corp
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Filing: 1987-12-30
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Granted: 1989-06-13
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Expires: 2007-12-30
Abstract
Abstract An early failure detection system for a multiprocessor system has a plurality of central processing units. When an idling central processing unit is detected by a microprogram stored in a control memory or a control memory controller, a test program for testing the idling central processing unit is executed before the idling central processing unit becomes busy. The test program is read out from a main memory and is executed using a register, an arithmetic circuit, an instruction advance fetching and decoding circuit, a main memory access control circuit, and the like. If a hardware failure of the idling central processing unit occurs during execution of the test program, the failed central processing unit is separated from the system so that the system can continue operation.
Inventors
- 👤 Akihisa Makita
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 16:04
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/22; G06F11/2205; G06F11/2236; G06F11/2242; G06F11/07; G06F11/16; G06F11/20; G06F11/26; G06F11/273; G06F11/2736
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
191 words
An early failure detection system for a multiprocessor system having a plurality of central processing units for microprogram control, said early failure detection system comprising: idle detecting means for detecting that at least one of said plurality of central processing units is idling; a main memory, commonly connected to said plurality of central processing units, said main memory storing a test program which begins operation when idling of said at least one idling central processing unit is detected by said idle detecting means and which detects a hardware failure of said at least one idling central processing unit before said at least one idling central processing unit becomes busy; reading means for reading out said test program from said main memory and for executing said test program during idling of said at least one central processing unit; and separating means, responsive to a failure of said at least one idling central processing unit during execution of said test program, for separating all failed central processing units from said multiprocessor system so as to allow at least one remaining central processing unit to operate, thereby maintaining continuous operation of said multiprocessor system.
Claim 2
Dependent Claim
191 words
An early failure detection system for a multiprocessor system having a plurality of central processing units for microprogram control, said early failure detection system comprising: idle detecting means for detecting that at least one of said plurality of central processing units is idling; a main memory, commonly connected to said plurality of central processing units, said main memory storing a test program which begins operation when idling of said at least one idling central processing unit is detected by said idle detecting means and which detects a hardware failure of said at least one idling central processing unit before said at least one idling central processing unit becomes busy; reading means for reading out said test program from said main memory and for executing said test program during idling of said at least one central processing unit; and separating means, responsive to a failure of said at least one idling central processing unit during execution of said test program, for separating all failed central processing units from said multiprocessor system so as to allow at least one remaining central processing unit to operate, thereby maintaining continuous operation of said multiprocessor system.
Claim 3
Dependent Claim
99 words
An early failure detection system according to claim 1, wherein each of said plurality of central processing units includes a main memory access control circuit performing access control to said main memory, an instruction advance fetching and decoding circuit fetching an instruction in advance and decoding an instruction code, an arithmetic circuit performing various arithmetic operations, a microprogram control section having a control memory which stores a microprogram, and a control memory controller decoding said microprogram read out from said control memory and sending a control signal to said arithmetic circuit, said idle detecting means, and said reading means.
Claim 4
Dependent Claim
166 words
An early failure detection system for a multiprocessor system having a plurality of central processing units for microprogram control, said early failure detection system comprising: idling detecting means for detecting that at least one of said plurality of central processing unit is idling; a control memory storing a test microprogram which is started when idling of said at least one central processing unit is detected by said idling detecting means and which detects a hardware failure of said at least one idling central processing unit before said at least one idling central processing unit becomes busy; reading means for reading out said test microprogram from said control memory and for executing said test microprogram; and separating means for separating all failed central processing units from said multiprocessor system when a failure of said at least one idling central processing unit occurs during execution of said test microprogram to allow at least one remaining central processing unit to operate, thereby maintaining continuous operation of said multiprocessor system.
Claim 5
Dependent Claim
166 words
An early failure detection system for a multiprocessor system having a plurality of central processing units for microprogram control, said early failure detection system comprising: idling detecting means for detecting that at least one of said plurality of central processing unit is idling; a control memory storing a test microprogram which is started when idling of said at least one central processing unit is detected by said idling detecting means and which detects a hardware failure of said at least one idling central processing unit before said at least one idling central processing unit becomes busy; reading means for reading out said test microprogram from said control memory and for executing said test microprogram; and separating means for separating all failed central processing units from said multiprocessor system when a failure of said at least one idling central processing unit occurs during execution of said test microprogram to allow at least one remaining central processing unit to operate, thereby maintaining continuous operation of said multiprocessor system.
Claim 6
Dependent Claim
97 words
An early failure detection system according to claim 3, wherein each of said plurality of central processing units includes a main memory access control circuit performing access control to said main memory, an instruction advance fetching and decoding circuit fetching an instruction in advance and decoding an instruction code, an arithmetic circuit performing various arithmetic operations, a microprogram control section having a control memory which stores a microprogram including said test microprogram, and a control memory controller decoding said microprogram and sending a control signal to said arithmetic circuit, said idling detecting means, and said reading means.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-06-12 | 1992-12-12 | 1993-06-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-06-12 | 1996-12-12 | 1997-06-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-06-12 | 2000-12-12 | 2001-06-13 | $7700.00 | Window Closed / Lapsed |