Contiguous channel multiplexer/demultiplexer

Claim 3

An apparatus as in claim 1, wherein: (a) said signal dividing means divides said input signal into N equiphase samples, each of said samples being expressed as e.sub.n =A.sub.n cos ωt where n is any sample, A is a constant, ω is a radian frequency, and t is time; (b) said delaying means delays each said sample by a delay T n relative to other said samples, said first arithmetic progression being expressed as: ##EQU9## where n=(N+1)/2, and Δf represents a bandwidth for separating each frequency channel output from said apparatus, said first arithmetic progression providing a first phase shift of each said sample relative to each other said sample, said first phase shift varying linearly with frequency at a progressively increasing slope from first of said samples to last of said samples, said first phase shift being expressed as ##EQU10## (c) said phase shifting means provides a second phase shift to each said sample relative to other said samples, said second arithmetic progression being expressed as ##EQU11## where C is the fractional part of numerical quantity (n+f 1 /Δf) and f 1 is the center frequency of the lowest frequency channel of said input signal; and (d) said combining means divides an nth said sample into N equal parts, provides a third phase shift to each of said N equal parts, and combines each of said N equal parts with corresponding parts from each other sample for forming a sum e m , where m is any output of said combining means, said third phase shift being expressed as: ##EQU12## and said sum e m being expressed as ##EQU13##

Claim 4

An apparatus as in claim 2 wherein said signal dividing means includes a power divider.

Claim 5

An apparatus as in claim 3 wherein said power divider includes an input port and a plurality of output ports, said plurality of output ports being at least equal in quantity to said plurality of samples, each said output port being designated as a number in arithmetic progression.

Claim 6

An apparatus as in claim 2 wherein said delaying means includes a plurality of delay lines, an nth delayed sample being expressed as ##EQU14##

Claim 7

An apparatus as in claim 5 wherein said plurality of delay lines is at least equal in quantity to said plurality of samples, each delay line being designated by a number in arithmetic progression, each said number further designating an output port of said signal dividing means, each delay line being coupled to an output port, each said coupled delay line and output port being designated by the same said number, and the delay of each delay line includes a common difference in delay relative to each succeeding delay line, said common difference in delay being equal to a reciprocal of the product of the plurality of said samples multiplied by said bandwidth for separating each frequency channel output from said apparatus.

Claim 8

An apparatus as in claim 2 wherein said phase shifting means includes a plurality of phase shift networks, an nth delayed and phase shifted sample bieng expressed as ##EQU15##

Claim 9

An apparatus as in claim 7 wherein said plurality of phase shift networks is at least equal in quantity to said plurality of samples, each phase shift network being designated by a number in arithmetic progression, each said number further designating an output of said delaying means, each phase shift network being coupled to an output of said delaying means, each said coupled phase shift network and output of said delaying means being designated by the same said number.

Claim 10

An apparatus as in claim 2 wherein said combining means comprises a Butler matrix.

Claim 11

An apparatus as in claim 9 wherein said Butler matrix includes a plurality of input ports, said plurality of input ports being at least equal in quantity to said plurality of samples, each input port being coupled to an outport port of said phase shifting means, said Butler matrix having a plurality of output ports being at least equal in quantity to said plurality of input ports, and said Butler matrix combines said samples at different output ports of said Butler matrix for achieving constructive nearly in-phase addition of samples, and for achieving destructive nearly out-of-phase addition of samples, said constructive nearly in-phase addition of samples forming an output signal.

Claim 12

A multiplexer/demultiplexer comprising: means for performing at least one of a multiplex operation or demultiplex operation, said means for performing a demultiplex operation including: (a) signal dividing means for forming a plurality of samples of an input signal, said signal dividing means dividing said input signal into N equiphase samples, each of said samples being expressed as e.sub.n =A.sub.n cos ωt where n is any sample, A is a constant, ω is a radian frequency, and t is time; (b) delaying means coupled to said signal dividing means for non-dispersively, differentially delaying each of said samples in accordance with a first arithmetic progression, said delaying means delaying each said sample by a delay T n relative to other said samples, said first arithmetic progression being expressed as: ##EQU16## where n=(N+1)/2, and Δf represents a bandwidth for separating each frequency channel output from said apparatus, said first arithmetic progression providing a first phase shift of each said sample relative to each other said sample, said first phase shift varying linearly with frequency at a progressively increasing slope from first of said samples to last of said samples, said first phase shift being expressed as ##EQU17## (c) phase shifting means coupled to said delaying means for phase shifting each of said samples in accordance with a second arithmetic progression, said phase shifting means providing a second phase shift to each said sample relative to other said samples, said second arithmetic progression being expressed as ##EQU18## where C is the fractional part of numerical quantity (n+f 1 /Δf) and f 1 is the center frequency of the lowest frequency channel of said input signal; and (d) combining means coupled to said phase shifting means for combining approximately in-phase samples, said combined samples forming an output signal, said combining means dividing an nth said sample into N equal parts, providing a third phase shift to each of said N equal parts, and combining each of said N equal parts with corresponding parts from each other sample for forming a sum e m where m is any output of said combining means, said third phase shift being expressed as: ##EQU19## and said sum e m being expressed as ##EQU20## and said means for performing a multiplex operation including said signal dividing means, said delaying means, said phase shifting means, and said combining means, whereby said signal dividing means, said delaying means, said phase shifting means, and said combining means are coupled as in a demultiplex operation and perform in a reciprocal manner of said demultiplex operation.

Claim 13

A multiplexer/demultiplexer comprising: means for performing at least one of a multiplex operation or demultiplex operation, said means for performing a demultiplex operation including: (a) signal dividing means for forming a plurality of samples of an input signal, said signal dividing means dividing said input signal into N equiphase samples, each of said samples being expressed as e.sub.n =A.sub.n cos ωt where n is any sample, A is a constant, ω is a radian frequency, and t is time; (b) delaying means coupled to said signal dividing means for non-dispersively, differentially delaying each of said samples in accordance with a first arithmetic progression, said delaying means delaying each said sample by a delay T n relative to other said samples, said first arithmetic progression being expressed as: ##EQU16## where n=(N+1)/2, and Δf represents a bandwidth for separating each frequency channel output from said apparatus, said first arithmetic progression providing a first phase shift of each said sample relative to each other said sample, said first phase shift varying linearly with frequency at a progressively increasing slope from first of said samples to last of said samples, said first phase shift being expressed as ##EQU17## (c) phase shifting means coupled to said delaying means for phase shifting each of said samples in accordance with a second arithmetic progression, said phase shifting means providing a second phase shift to each said sample relative to other said samples, said second arithmetic progression being expressed as ##EQU18## where C is the fractional part of numerical quantity (n+f 1 /Δf) and f 1 is the center frequency of the lowest frequency channel of said input signal; and (d) combining means coupled to said phase shifting means for combining approximately in-phase samples, said combined samples forming an output signal, said combining means dividing an nth said sample into N equal parts, providing a third phase shift to each of said N equal parts, and combining each of said N equal parts with corresponding parts from each other sample for forming a sum e m where m is any output of said combining means, said third phase shift being expressed as: ##EQU19## and said sum e m being expressed as ##EQU20## and said means for performing a multiplex operation including said signal dividing means, said delaying means, said phase shifting means, and said combining means, whereby said signal dividing means, said delaying means, said phase shifting means, and said combining means are coupled as in a demultiplex operation and perform in a reciprocal manner of said demultiplex operation.

Claim 14

A multiplexer/demultiplexer as in claim 11 wherein: (a) said signal dividing means includes a power divider in said demultiplex operation, said power divider being a power combiner in said multiplex operation, said power divider having an input port and a plurality of output ports, said plurality of output ports being at least equal in quantity to said plurality of samples, each said output port being designated as a number in arithmetic progression: (b) said delaying means includes a plurality of delay lines, an nth delayed sample being expressed as ##EQU21## said plurality of delay lines being at least equal in quantity to said plurality of samples, each delay line being designated by a number in arithmetic progression, each said number further designating an output port of said signal dividing means, each delay line being coupled to an output port, each said coupled delay line and output port being designated by the same said number, and the delay of each delay line includes a common difference in delay relative to each succeeding delay line, said common difference in delay being equal to a reciprocal of the product of the plurality of said samples multiplied by said bandwidth for separating each frequency channel output from said apparatus; (c) said phase shifting means includes a plurality of phase shift networks, an nth delayed and phase shifted sample being expressed as ##EQU22## said plurality of phase shift networks being at least equal in quantity to said plurality of samples, each phase shift network being designated by a number in arithmetic progression, each said number further designating an output of said delaying means, each phase shift network being coupled to an output of said delaying means, each said coupled phase shift network and output of said delaying means being designated by the same said number; and (d) said combining means includes a Butler matrix, said Butler matrix having a plurality of input ports, said plurality of input ports being at least equal in quantity to said plurality of samples, each input port being coupled to an output port of said phase shifting means, said Butler matrix having a plurality of output ports being at least equal in quantity to said plurality of input ports, and said Butler matrix combines said samples at different output ports of said Butler matrix for achieving constructive nearly in-phase addition of samples, and for achieving destructive nearly out-of-phase addition of samples, said constructive nearly in-phase addition of samples forming an output signal.