High density associative memory

Claim 1

A multi-layered, thin-film, digital memory comprising: (a) a first layer comprising a plurality of electrically separated row conductors; (b) a second layer comprising a plurality of electrically separated column conductors intersect electrically separated from said row conductors; and, (c) a plurality of resistance elements electrically connected between said row conductors and said column conductors at respective intersections of said row conductors and said column conductors, each resistance element comprising, in series, a first resistor of sufficiently high ohmage to conduct a sensible current therethrough with virtually no heat-generating power consumption when a low voltage as employed in thin-film applications is applied thereacross and a second resistor of sufficiently high ohmage to conduct no sensible current therethrough when a low voltage as employed in thin-film applications is applied thereacross, said second resistor having the quality of breaking down to create a short therethrough upon the application of a breakdown level voltage across said second resistor.

Claim 9

The method of forming and writing into a multi-layered, thin-film, read-only, digital memory comprising: (a) forming a first layer comprising a plurality of electrically separated row conductors; (b) forming a second layer comprising a plurality of electrically separated column conductors intersecting but electrically separated from the row conductors; (c) forming a plurality of resistance elements electrically connected between the row conductors and the column conductors at respective intersections of the row conductors and the column conductors wherein each resistance element comprises, in series, a first resistor of sufficiently high ohmage to conduct a sensible current therethrough with virtually no heat-generating power consumption when a low voltage as employed in thin-film applications is applied thereacross and a second resistor of sufficiently high ohmage to conduct no sensible current therethrough when a low voltage as employed in thin-film applications is applied thereacross; and, (d) writing data into the memory by applying a voltage across each second resistor wherein there is to be a binary "1" sufficiently high so as to break down that second resistor and create a short therethrough.

Claim 10

The method of forming and writing into a multi-layered, thin-film, read-only, digital memory comprising: (a) forming a first layer comprising a plurality of electrically separated row conductors; (b) forming a second layer comprising a plurality of electrically separated column conductors intersecting but electrically separated from the row conductors; (c) forming a plurality of resistance elements electrically connected between the row conductors and the column conductors at respective intersections of the row conductors and the column conductors wherein each resistance element comprises, in series, a first resistor of sufficiently high ohmage to conduct a sensible current therethrough with virtually no heat-generating power consumption when a low voltage as employed in thin-film applications is applied thereacross and a second resistor of sufficiently high ohmage to conduct no sensible current therethrough when a low voltage as employed in thin-film applications is applied thereacross; and, (d) writing data into the memory by applying a voltage across each second resistor wherein there is to be a binary "1" sufficiently high so as to break down that second resistor and create a short therethrough.

Claim 12

The method of constructing, writing to, and reading from a multi-layered, thin-film, digital memory with associative recall comprising the steps of: (a) constructing a first memory matrix and a second memory matrix, the construction of each matrix comprising the steps of, (a1) forming a first layer comprising a plurality of electrically separated row conductors; (a2) forming a second layer comprising a plurality of electrically separated column conductors intersecting but electrically separated from the row conductors; and, (a3) forming a plurality of resistance elements electrically connected between the row conductors and the column conductors at respective intersections of the row conductors and the column conductors wherein each resistance element comprises, in series, a first resistor of sufficiently high ohmage to conduct a sensible current therethrough with virtually no heat-generating power consumption when a low voltage as employed in thin-film applications is applied thereacross and a second resistor of sufficiently high ohmage to conduct no sensible current therethrough when a low voltage as employed in thin-film applications is applied thereacross; (b) writing output data into the second memory matrix by applying a voltage across each second resistor thereof wherein there is to be a binary "1" sufficiently high so as to break down that second resistor and create a short therethrough; (c) writing associative input data into the first memory matrix by applying a voltage across each second resistor thereof wherein there is to be a binary "1" sufficiently high so as to break down that second resistor and create a short therethrough; (d) connecting the inputs of a plurality of bi-stable sense amplifiers to respective ones of the column conductors of the second matrix to indicate at outputs thereof when a current flow is detected at the input in the one of the column conductors of the second matrix connected thereto; (e) connecting the outputs of a plurality of current summing amplifiers to respective ones of the row conductors of the second matrix to apply a voltage to the one of the row conductors of the second matrix connected thereto when the current into a second input thereof exceeds the current into a first input thereof; (f) electrically connecting respective ones of the row conductors of the first matrix to the second inputs; (g) connecting the outputs of a plurality of bi-stable read drivers to respective ones of the column conductors of the first matrix to output a voltage when an input thereof has a binary "1" prompt value applied thereto and to not output a voltage when the input thereof has a binary "0" prompt value applied thereto; (h) applying a prompt value to be used for associative recall to the inputs of the plurality of read drivers; (i) connecting the output of a ramped read driver to the first inputs of the current summing amplifiers and producing a downward ramp at the output thereof starting at a value higher than the maximum possible value at the second inputs and decreasing until one of the current summing amplifiers has its second input value higher than the output of the ramped read driver and applies a voltage to the one of the row conductors of the second matrix connected thereto; and, (j) reading the contents of the associated word in the second memory matrix at the outputs of the sense amplifiers.

Claim 13

The method of constructing, writing to, and reading from a multi-layered, thin-film, digital memory with associative recall comprising the steps of: (a) constructing a first memory matrix and a second memory matrix, the construction of each matrix comprising the steps of, (a1) forming a first layer comprising a plurality of electrically separated row conductors; (a2) forming a second layer comprising a plurality of electrically separated column conductors intersecting but electrically separated from the row conductors; and, (a3) forming a plurality of resistance elements electrically connected between the row conductors and the column conductors at respective intersections of the row conductors and the column conductors wherein each resistance element comprises, in series, a first resistor of sufficiently high ohmage to conduct a sensible current therethrough with virtually no heat-generating power consumption when a low voltage as employed in thin-film applications is applied thereacross and a second resistor of sufficiently high ohmage to conduct no sensible current therethrough when a low voltage as employed in thin-film applications is applied thereacross; (b) writing output data into the second memory matrix by applying a voltage across each second resistor thereof wherein there is to be a binary "1" sufficiently high so as to break down that second resistor and create a short therethrough; (c) writing associative input data into the first memory matrix by applying a voltage across each second resistor thereof wherein there is to be a binary "1" sufficiently high so as to break down that second resistor and create a short therethrough; (d) connecting the inputs of a plurality of bi-stable sense amplifiers to respective ones of the column conductors of the second matrix to indicate at outputs thereof when a current flow is detected at the input in the one of the column conductors of the second matrix connected thereto; (e) connecting the outputs of a plurality of current summing amplifiers to respective ones of the row conductors of the second matrix to apply a voltage to the one of the row conductors of the second matrix connected thereto when the current into a second input thereof exceeds the current into a first input thereof; (f) electrically connecting respective ones of the row conductors of the first matrix to the second inputs; (g) connecting the outputs of a plurality of bi-stable read drivers to respective ones of the column conductors of the first matrix to output a voltage when an input thereof has a binary "1" prompt value applied thereto and to not output a voltage when the input thereof has a binary "0" prompt value applied thereto; (h) applying a prompt value to be used for associative recall to the inputs of the plurality of read drivers; (i) connecting the output of a ramped read driver to the first inputs of the current summing amplifiers and producing a downward ramp at the output thereof starting at a value higher than the maximum possible value at the second inputs and decreasing until one of the current summing amplifiers has its second input value higher than the output of the ramped read driver and applies a voltage to the one of the row conductors of the second matrix connected thereto; and, (j) reading the contents of the associated word in the second memory matrix at the outputs of the sense amplifiers.