Patent US4839704A successfully refreshed from Google Patents.
US4839704A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Application of deep-junction non-self-aligned transistors for suppressing hot carriers
Assignee: National Semiconductor Corp
•
Filing: 1987-09-16
•
Granted: 1989-06-13
•
Expires: 2007-09-16
Abstract
Abstract A structure and method of fabricating same is provided for a deep junction, non-self-aligned MOS transistor for suppressing hot carrier injection. According to the invention, dopant is introduced into a semiconductor substrate of a first conductivity type to form first and second spaced-apart substrate regions of opposite conductivity in the substrate. The first and second regions will become the source and drain regions of a deep junction, non-self-aligned MOS transistor having an effective channel length less than about 3.5 microns. The junction depth of the source and drain regions is greater than about 4000 Angstroms. Next, a layer of dielectric material is formed over the substrate. A region of conductive material is then formed over the dielectric material to serve as the gate of the MOS device. The resulting deep junction device has improved reliability as compared to self-aligned MOS devices of comparable effective channel length.
Inventors
- 👤 Farrokh Mohammadi
- 👤 Chin-Miin Shyu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 09:18
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
110 words
A deep junction MOS transistor for suppressing hot carrier injection comprising: (a) first and second spaced apart regions of a first conductivity type formed in a semiconductor substrate of a conductivity type opposite to the first conductivity type to define a channel region therebetween, the effective channel length being less than about 3.5 microns, the junction depth of the first and second regions being greater than about 4000 Angstroms; (b) a layer of dielectric material formed on the channel region; (c) a region of conductive material formed on the layer of dielectric material overlying the channel region, wherein the region of conductive material forms a non-self-aligned gate of the transistor.
Claim 2
Dependent Claim
110 words
A deep junction MOS transistor for suppressing hot carrier injection comprising: (a) first and second spaced apart regions of a first conductivity type formed in a semiconductor substrate of a conductivity type opposite to the first conductivity type to define a channel region therebetween, the effective channel length being less than about 3.5 microns, the junction depth of the first and second regions being greater than about 4000 Angstroms; (b) a layer of dielectric material formed on the channel region; (c) a region of conductive material formed on the layer of dielectric material overlying the channel region, wherein the region of conductive material forms a non-self-aligned gate of the transistor.
Claim 3
Dependent Claim
16 words
A deep junction MOS transistor as in claim 1 wherein the first conductivity type is N-type.
Claim 4
Dependent Claim
19 words
A deep junction MOS junction transistor as in claim 2 wherein the effective channel length is about 3.3 microns.
Claim 5
Dependent Claim
17 words
A deep junction MOS transistor as in claim 3 wherein the junction depth is about 0.5-1.4 microns.
Claim 6
Dependent Claim
15 words
A deep junction MOS transistor as in claim 1 wherein the conductive material is polysilicon.
Claim 7
Dependent Claim
138 words
Integrated circuitry comprising (a) first, second and third spaced-apart regions of N-type conductivity formed in a semi-conductor substrate of P-type conductivity, the first N-type region defining the lower plate of an MOS capacitor, the second and third N-type regions defining the source and drain regions, respectively, of an MOS transistor and further defining a channel region therebetween, the effective channel length being less than about 3.5 microns, the junction depth of the second and third regions being greater than about 4000 Angstroms; (b) a layer of dielectric material formed on the substrate overlying the first, second and third N-type regions; (c) first and second regions of conductive material formed on the dielectric material overlying the first N-type region and the channel region, respectively, wherein the second region of conductive material forms a non-self-aligned gate of the MOS transfer.
Claim 8
Dependent Claim
138 words
Integrated circuitry comprising (a) first, second and third spaced-apart regions of N-type conductivity formed in a semi-conductor substrate of P-type conductivity, the first N-type region defining the lower plate of an MOS capacitor, the second and third N-type regions defining the source and drain regions, respectively, of an MOS transistor and further defining a channel region therebetween, the effective channel length being less than about 3.5 microns, the junction depth of the second and third regions being greater than about 4000 Angstroms; (b) a layer of dielectric material formed on the substrate overlying the first, second and third N-type regions; (c) first and second regions of conductive material formed on the dielectric material overlying the first N-type region and the channel region, respectively, wherein the second region of conductive material forms a non-self-aligned gate of the MOS transfer.
Claim 9
Dependent Claim
15 words
Integrated circuitry as in claim 6 wherein the effective channel length is about 3.3 microns.
Claim 10
Dependent Claim
14 words
Integrated circuitry as in claim 7 wherein the junction depth is about 0.5-1.4 microns.
Claim 11
Dependent Claim
26 words
Integrated circuitry as in claim 8 wherein the dielectric material comprises an oxide of silicon and the first and second regions of conductive material comprise polysilicon.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-06-12 | 1992-12-12 | 1993-06-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-06-12 | 1996-12-12 | 1997-06-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-06-12 | 2000-12-12 | 2001-06-13 | $7700.00 | Window Closed / Lapsed |