Patent US4837767A successfully refreshed from Google Patents.
US4837767A
Expired / Lapsed
US
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Bus adapter module with improved error recovery in a multibus computer system
Assignee: Hewlett Packard Development Co LP
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Filing: 1987-09-04
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Granted: 1989-06-06
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Expires: 2007-09-04
Abstract
Abstract A bus adapter interconnecting a system bus and an I/O bus over an interconnect bus generates a first READ signal by decoding the command lines of the I/O bus and supplying the READ command signal across the interconnect bus. The command lines are also provided across the interconnect bus and are decoded on the system bus side of the interconnect bus to form a second READ signal. The first and second READ signals and a parity error signal are processed on the system bus side of the interconnect bus to generate a NON-RECOVERABLE ERROR signal to initiate a system shut-down when a parity error occurs during a disconnected WRITE transaction and to generate a RECOVERABLE ERROR signal to initiate a repeat of the transaction when a parity error occurs during a READ transaction.
Inventors
- 👤 David W. Hartwell
- 👤 Elbert Bloom
- 👤 Victoria M. Triolo
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 21:31
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/14; G06F11/1402; G06F11/1405; G06F11/141; G06F11/08; G06F11/10
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
199 words
A control adapter module providing error recovery in a computer system including a first bus, connected to an interconnect bus through a response adapter module, and a second bus, the second bus having a plurality of data lines and a plurality of command lines carrying command signals to initiate execution of a plurality of types of transactions on the second bus, the response module including a logic circuit asserting a RECOVERABLE ERROR signal when a parity error occurs during a READ transaction and asserting a NON-RECOVERABLE ERROR signal when a parity error occurs during a WRITE transaction to initiate a system shut-down, the control adapter module comprising: an interconnect interface circuit adapted for connection to the interconnect bus; a bus interface circuit connected to the interconnect interface circuit and adapted for connection to the second bus; decoder means connected to the bus interface circuit and responsive to command signals on the command lines for asserting a command type signal and for supplying the command type signal to the interconnect interface circuit; and control means responsive to the RECOVERABLE ERROR signal for asserting a signal on the second bus indicating unsuccessful execution of the current transaction on the second bus.
Claim 2
Dependent Claim
199 words
A control adapter module providing error recovery in a computer system including a first bus, connected to an interconnect bus through a response adapter module, and a second bus, the second bus having a plurality of data lines and a plurality of command lines carrying command signals to initiate execution of a plurality of types of transactions on the second bus, the response module including a logic circuit asserting a RECOVERABLE ERROR signal when a parity error occurs during a READ transaction and asserting a NON-RECOVERABLE ERROR signal when a parity error occurs during a WRITE transaction to initiate a system shut-down, the control adapter module comprising: an interconnect interface circuit adapted for connection to the interconnect bus; a bus interface circuit connected to the interconnect interface circuit and adapted for connection to the second bus; decoder means connected to the bus interface circuit and responsive to command signals on the command lines for asserting a command type signal and for supplying the command type signal to the interconnect interface circuit; and control means responsive to the RECOVERABLE ERROR signal for asserting a signal on the second bus indicating unsuccessful execution of the current transaction on the second bus.
Claim 3
Dependent Claim
187 words
Apparatus for error recovery in a computer system including including a first bus, connected to an interconnect bus through a response adapter module, and a second bus, the second bus having a plurality of data lines and a plurality of command lines indicating READ and WRITE commands present on the second bus, the response module including a logic circuit asserting a RECOVERABLE ERROR signal when a parity error occurs during a READ transaction and asserting a NON-RECOVERABLE ERROR signal when a parity error occurs during a WRITE transaction to initiate a system shut-down, the apparatus comprising; an interconnect interface circuit adapted for connection to the interconnect bus; a bus interface circuit connected to the interconnect interface circuit and adapted for connection to the second bus; decoder means connected to the second bus interface circuit and responsive to command signals on the command lines for asserting a READ signal and for supplying the READ signal to the interconnect interface circuit; and control means responsive to the RECOVERABLE ERROR signal for asserting a signal on the second bus indicating unsuccessful execution of a READ transaction on the second bus.
Claim 4
Dependent Claim
187 words
Apparatus for error recovery in a computer system including including a first bus, connected to an interconnect bus through a response adapter module, and a second bus, the second bus having a plurality of data lines and a plurality of command lines indicating READ and WRITE commands present on the second bus, the response module including a logic circuit asserting a RECOVERABLE ERROR signal when a parity error occurs during a READ transaction and asserting a NON-RECOVERABLE ERROR signal when a parity error occurs during a WRITE transaction to initiate a system shut-down, the apparatus comprising; an interconnect interface circuit adapted for connection to the interconnect bus; a bus interface circuit connected to the interconnect interface circuit and adapted for connection to the second bus; decoder means connected to the second bus interface circuit and responsive to command signals on the command lines for asserting a READ signal and for supplying the READ signal to the interconnect interface circuit; and control means responsive to the RECOVERABLE ERROR signal for asserting a signal on the second bus indicating unsuccessful execution of a READ transaction on the second bus.
Claim 5
Dependent Claim
44 words
Apparatus as recited in claim 2 wherein the command lines carry signals indicating a plurality of types of READ commands, and wherein the decoder means comprises means for asserting the READ signal upon detection of signals indicating any of the plurality of READ commands.
Claim 6
Dependent Claim
45 words
Apparatus as recited in claim 2 wherein the command lines carry signals indicating a plurality of types of WRITE commands and the decoder means comprises means for asserting a READ signal upon detection of signals indicating a command other than a WRITE or INTERRUPT command.
Claim 7
Independent Claim
149 words
A method for error recovery in a computer system including a first bus, connected to an interconnect bus through a response adapter module, and a second bus, the second bus having a plurality of data lines and a plurality of command lines carrying command signals to initiate execution of a plurality of types of transactions on the second bus, the response module including a logic circuit asserting a RECOVERABLE ERROR signal when a parity error occurs during a READ transaction and asserting a NON-RECOVERABLE ERROR signal when a parity error occurs during a WRITE transaction to initiate a system shut-down, the method comprising the steps of: decoding the command signals from the second bus to generate a READ signal; supplying the READ signal and bus signals from the second bus to the interconnect bus; and initiating a repeat of a READ transaction in response to a RECOVERABLE ERROR signal.
Claim 8
Independent Claim
149 words
A method for error recovery in a computer system including a first bus, connected to an interconnect bus through a response adapter module, and a second bus, the second bus having a plurality of data lines and a plurality of command lines carrying command signals to initiate execution of a plurality of types of transactions on the second bus, the response module including a logic circuit asserting a RECOVERABLE ERROR signal when a parity error occurs during a READ transaction and asserting a NON-RECOVERABLE ERROR signal when a parity error occurs during a WRITE transaction to initiate a system shut-down, the method comprising the steps of: decoding the command signals from the second bus to generate a READ signal; supplying the READ signal and bus signals from the second bus to the interconnect bus; and initiating a repeat of a READ transaction in response to a RECOVERABLE ERROR signal.
Claim 9
Dependent Claim
31 words
A method as recited in claim 5 wherein the step of initiating a repeat of a READ transaction comprises the substep of placing a no-acknowledge confirmation signal on the second bus.
Claim 10
Dependent Claim
37 words
A method as recited in claim 5 wherein the step of supplying the READ signal and bus signals from the second bus comprises the substep of supplying command signals from the second bus to the interconnect bus.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-06-05 | 1992-12-05 | 1993-06-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-06-05 | 1996-12-05 | 1997-06-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-06-05 | 2000-12-05 | 2001-06-06 | $7700.00 | Window Closed / Lapsed |