Patent US4837748A successfully refreshed from Google Patents.
US4837748A
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Counting RAM
Assignee: Promos Technologies Inc
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Filing: 1987-04-14
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Granted: 1989-06-06
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Expires: 2007-04-14
Abstract
Abstract An integrated circuit memory with additional circuitry added so that the integrated circuit acts as a counting memory is disclosed. A memory core is included with associated circuitry allowing it to be accessed in the same manner as ordinary random access memory (RAM). A counter is included and is coupled so that it can receive the contents of any location in the memory core. Each address in the memory acts as an individual counter. When a particular memory address is presented indicating that the count at that memory location should be incremented, the contents of that memory location are transferred to the counter, the counter is incremented, and the contents of the counter are then transferred back to the memory location. This process is repeated each time a new address is presented indicating a new event to be recorded. At the end of a series of events, the core memory will contain, at each corresponding memory location, the number of occurrences of the event assigned to that address.
Inventors
- 👤 Shine C. Chung
- 👤 Siu K. Tsang
- 👤 James T. Koo
- 👤 Sho Long S. Chen
- 👤 John Y. Chan
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 22:55
CPC Classifications
G; G11; G11C; G11C8/00; G11C16/00; G11C16/02; G11C16/06; G11C16/10; G11C16/102; G11C8/04
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
57 words
An integrated electronic circuit comprising: a memory having a plurality of addressable locations; a counter; control means for first providing the contents of an addressed one of said memory locations to said counter as the count of said counter, second, directing said counter to change said count, and third, returning said changed count to said memory location.
Claim 2
Dependent Claim
57 words
An integrated electronic circuit comprising: a memory having a plurality of addressable locations; a counter; control means for first providing the contents of an addressed one of said memory locations to said counter as the count of said counter, second, directing said counter to change said count, and third, returning said changed count to said memory location.
Claim 3
Dependent Claim
23 words
The circuit of claim 1 further comprising an overflow detector for detecting an overflow of said counter and providing an output overflow signal.
Claim 4
Dependent Claim
77 words
The circuit of claim 1 wherein said counter holds at least twice as many bits as each said memory location and further comprising: demultiplexing means for providing the contents of at least first and second succeeding memory locations to first and second portions of said counter; and multiplexing means for providing the contents of said first portion of said counter to said first memory location and said second portion of said counter to said second memory location.
Claim 5
Dependent Claim
30 words
The circuit of claim 1 wherein said control means includes means, responsive to a first control signal, for disabling said counter so that said circuit functions solely as a memory.
Claim 6
Dependent Claim
43 words
The circuit of claim 1 wherein said control means includes means for incrementing said count of said counter responsive to a first state of a control signal and decrementing said count of said counter responsive to a second state of said control signal.
Claim 7
Dependent Claim
164 words
An integrated electronic circuit comprising: a memory having a plurality of addressable locations; a counter, said counter holding at least twice as many bits as each said memory location; control means for first, providing the contents of an addressed one of said memory locations to said counter as the count of said counter, second, directing said counter to change said count, and third, returning said changed count to said memory location, said control means including means, responsive to a first control signal, for disabling said counter so that said circuit functions solely as a memory; an overflow detector for detecting an overflow of said counter and providing an overflow signal; demultiplexing means for providing the contents of at least first and second succeeding memory locations to first and second portions of said counter; and multiplexing means for providing the contents of said first portion of said counter to said first memory location and said second portion of said counter to said second memory location.
Claim 8
Dependent Claim
164 words
An integrated electronic circuit comprising: a memory having a plurality of addressable locations; a counter, said counter holding at least twice as many bits as each said memory location; control means for first, providing the contents of an addressed one of said memory locations to said counter as the count of said counter, second, directing said counter to change said count, and third, returning said changed count to said memory location, said control means including means, responsive to a first control signal, for disabling said counter so that said circuit functions solely as a memory; an overflow detector for detecting an overflow of said counter and providing an overflow signal; demultiplexing means for providing the contents of at least first and second succeeding memory locations to first and second portions of said counter; and multiplexing means for providing the contents of said first portion of said counter to said first memory location and said second portion of said counter to said second memory location.
Claim 9
Independent Claim
72 words
A method for maintaining a count of each occurrence of an event in a series of events using a random access memory and a counter, comprising the steps of: first, addressing a memory location corresponding to an event; second, transferring the contents of said memory location to said counter; third, changing the count of the contents of said counter; and fourth, transferring the contents of said counter back to said memory location.
Claim 10
Independent Claim
72 words
A method for maintaining a count of each occurrence of an event in a series of events using a random access memory and a counter, comprising the steps of: first, addressing a memory location corresponding to an event; second, transferring the contents of said memory location to said counter; third, changing the count of the contents of said counter; and fourth, transferring the contents of said counter back to said memory location.
Claim 11
Dependent Claim
16 words
The method of claim 7 further comprising the step of detecting an overflow of said counter.
Claim 12
Dependent Claim
65 words
The method of claim 7 wherein said counter holds at least twice as many bits as each memory location and further comprising the steps of transferring the contents of at least two succeeding memory locations to said counter prior to changing the contents of said counter and transferring the changed contents of a first and second portion of said counter to said succeeding address locations.
References Cited (Backward Citations)
US3832640A
Cited
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Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-06-05 | 1992-12-05 | 1993-06-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-06-05 | 1996-12-05 | 1997-06-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-06-05 | 2000-12-05 | 2001-06-06 | $7700.00 | Window Closed / Lapsed |