Digital to analog converter

Claim 2

A circuit for converting a binary number having bits, D 0 to D n , to an output signal having a proportionally equivalent characteristic, said circuit comprising: a parallel input for receiving each bit, D 0 to D n , of the binary number; means for generating wavetrains, W 0 to W n , having frequencies decreasing by powers of two from the least significant wavetrain, W 0 , to the most significant wavetrain, W n , each of said wavetrains comprising pulses having a pulse width equal to the inverse of twice the frequency of the least significant wavetrain, W 0 , so that the duty cycle of each of said wavetrains is proportional to the corresponding frequency thereof, and the pulses of each of said wavetrains are nonoverlapping with the pulses of others of said wavetrains; logic means, connected to said input and said generating means, for logically multiplying each of said wavetrains taken in an order from the least significant to the most significant, W 0 to W n , by a corresponding bit of the binary number taken in a reverse order from the most significant to the least significant, D n to D 0 , and logically summing all the products of each, the sum thereof being a composite waveform; and, output means, connected to said logic means, for receiving said composite waveform and for providing said output signal, in response thereto; whereby, said composite waveform has an amplitude equal to that of the pulses of said wavetrains and a duty cycle proportionally equivalent to the binary number.

Claim 3

A circuit as recited in claim 1, wherein said means for generating comprises: a donwcounter having outputs providing n signals, N 0 to N n , wherein the frequencies decrease by powers of two from the least significant downcounting signal, N 0 , to the most significant downcounting signal, N n ; and, decoder means, connected to the outputs of said downcounter, for inverting each downcounting signal, N 0 to N n , therefrom and logically multiplying each inverted downcounting signal by all of the corresponding less significant downcounting signals from said downcounter, the products therefrom forming said wavetrains, W 0 to W n .

Claim 4

A circuit as recited in claim 2, wherein said downcounter provides a timing signal, and wherein said output means further comprises synchronizing means for receiving said timing signal and synchronizing the edges of said composite waveform with the least significant downcounting signal (N 0 ) to elimiate the effects of propagation delays.

Claim 5

A circuit as recited in claim 3, wherein said synchronizing means comprises a D-type flip flop having a data terminal connected to said logic means and a toggle input connected to said downcounter for receiving the timing signal, the output of said flip flop providing said synchronized composite waveform.

Claim 6

A circuit as recited in claim 1, wherein said output means further comprises means for smoothing said composite waveform to provide an analog signal equal to the product of the amplitude and the duty cycle of said composite waveform, whereby said analog signal is proportionally equivalent to the binary number.

Claim 7

A circuit as recited in claim 5, wherein said means for smoothing is a low-pass filter.

Claim 8

A circuit as recited in claim 6 wherein said low-pass filter comprises a resistor and a capacitor, said resistor having one end connected to said logic means and the other end connected to the output of said circuit and said capacitor connected between ground and the output of said circuit, said analog signal being provided as said output signal.

Claim 9

A circuit as recited in claim 5, wherein said output means further comprising referencing means for referencing said composite waveform by setting a logic one level of said composite waveform to a precise reference voltage and a logic zero level of said composite waveform to a ground level, whereby said referencing means provides said composite waveform to said means for smoothing.

Claim 10

A circuit as recited in claim 8, wherein said referencing means comprises a PMOS FET and an NMOS FET, the gates of which are connected to receive said composite waveform, the drain terminal of said PMOS FET being connected to a positive precise reference voltage source, the source terminal of said NMOS FET being connected to ground, and the source terminal of said PMOS FET and the drain terminal of said NMOS FET both being connected to said means for smoothing.

Claim 11

A digital to analog converter for converting a binary number having bits, D 0 to D n , to an analog signal having a proportionally equivalent voltage, said converter comprising: a parallel input for receiving each bit, D 0 to D n , of the binary number: a downcounter having outputs providing downcounting signals, N 0 to N n , wherein the frequencies of said signals decrease by powers of two from the least significant downcounting signal, N 0 , to the most significant downcounting signal, N n ; decoder means, connected to the outputs of said downcounter, for inverting each downcounting signal, N 0 to N n , and logically multiplying each inverted downcounting signal by all of the corresponding less significant downcounting signals from said downcounter, the products therefrom forming wavetrains, W 0 to W n , having frequencies decreasing by powers of two from the least significant wavetrain, W 0 , to the most significant wavetrain, W n ; logic means, connected to said parallel input and said decoder means, for logically multiplying each of said wavetrains taken in an order from the least significant to the most significant, W 0 to W n , by a corresponding bit of the binary number taken in a reverse order from the most significant to the least significant, D n to D 0 , and logically summing all the products, the sum thereof being a composite waveform, consisting of each of said wavetrains enabled by said corresponding bits of said binary number and having a peak amplitude equal to that of the pulses of the wavetrains and a duty cycle proportionally equivalent to the binary number; and, means, connected to said logic means, for smoothing said composite waveform to provide said analog signal; whereby the analog signal is proportionally output equivalent to the binary numer and equal to the product of the amplitude and the duty cycle of said composite waveform.

Claim 12

A digital to analog converter for converting a binary number having bits, D 0 to D n , to an analog signal having a proportionally equivalent voltage, said converter comprising: a parallel input for receiving each bit, D 0 to D n , of the binary number: a downcounter having outputs providing downcounting signals, N 0 to N n , wherein the frequencies of said signals decrease by powers of two from the least significant downcounting signal, N 0 , to the most significant downcounting signal, N n ; decoder means, connected to the outputs of said downcounter, for inverting each downcounting signal, N 0 to N n , and logically multiplying each inverted downcounting signal by all of the corresponding less significant downcounting signals from said downcounter, the products therefrom forming wavetrains, W 0 to W n , having frequencies decreasing by powers of two from the least significant wavetrain, W 0 , to the most significant wavetrain, W n ; logic means, connected to said parallel input and said decoder means, for logically multiplying each of said wavetrains taken in an order from the least significant to the most significant, W 0 to W n , by a corresponding bit of the binary number taken in a reverse order from the most significant to the least significant, D n to D 0 , and logically summing all the products, the sum thereof being a composite waveform, consisting of each of said wavetrains enabled by said corresponding bits of said binary number and having a peak amplitude equal to that of the pulses of the wavetrains and a duty cycle proportionally equivalent to the binary number; and, means, connected to said logic means, for smoothing said composite waveform to provide said analog signal; whereby the analog signal is proportionally output equivalent to the binary numer and equal to the product of the amplitude and the duty cycle of said composite waveform.

Claim 13

A circuit as recited in claim 10, wherein said downcounter provides a timing signal, and wherein said circuit further comprises synchronizing means, connected to receive said composite waveform and said timing signal, for synchronizing the edges of said composite waveform with the least significant downcounting signal (N 0 ) to eliminate the effects of propagation delays.

Claim 14

A circuit as recited in claim 11, wherein said synchronizing means comprises a D-type flip flop having a data terminal connected to said logic means and a toggle input connected to said downcounter for receiving the timing signal, the output of said flip flop providing said synchronized composite waveform.

Claim 15

A circuit as recited in claim 10, wherein said means for smoothing is a low-pass filter.

Claim 16

A circuit as recited in claim 13 wherein said low-pass filter comprises a resistor and a capacitor, said resistor having one end connected to said logic means and the other end connected to the output of said circuit and said capacitor connected between ground and the output of said circuit, whereby the output of said circuit provides said analog signal.

Claim 17

A circuit as recited in claim 10, further comprising referencing means for referencing said composite waveform by setting a logic one level of said composite waveform to a precise reference voltage and a logic zero level of said composite waveform to a ground level, whereby said referencing means provides said composite waveform to said smoothing means.

Claim 18

A circuit as recited in claim 15, wherein said referencing means comprises a PMOS FET and an NMOS FET, the gates of which are connected to receive said composite waveform, the drain terminal of said PMOS FET being connected to a positive precise reference voltage source, the source terminal of said NMOS FET being connected to ground, and the source terminal of said PMOS FET and the drain of said NMOS FET both being connected to said means for smoothing.

Claim 19

A circuit for generating wavetrains, W 0 to W n , comprising: a downcounter having outputs providing downcounting signals, N 0 to N n , wherein the frequencies decrease by powers of two from the least significant downcounting signal, N 0 , to the most significant downcounting signal, N n ; decoder means, connected to the outputs of said downcounter, for inverting each downcounting signal, N 0 to N n , and logically multiplying each inverted downcounting signal by all of the corresponding less significant downcounting signals from said downcounter, the products therefrom forming the wavetrains, W 0 to W n , having pulses of equal pulse width; and output means, connected to said decoder means, for providing the wavetrains, W 0 to W n ; whereby, the duty cycle of each of said wavetrains is proportional to the corresponding frequency thereof and the pulses of said wavetrain are nonoverlapping with the pulses of other of said wavetrains.

Claim 20

A circuit for generating wavetrains, W 0 to W n , comprising: a downcounter having outputs providing downcounting signals, N 0 to N n , wherein the frequencies decrease by powers of two from the least significant downcounting signal, N 0 , to the most significant downcounting signal, N n ; decoder means, connected to the outputs of said downcounter, for inverting each downcounting signal, N 0 to N n , and logically multiplying each inverted downcounting signal by all of the corresponding less significant downcounting signals from said downcounter, the products therefrom forming the wavetrains, W 0 to W n , having pulses of equal pulse width; and output means, connected to said decoder means, for providing the wavetrains, W 0 to W n ; whereby, the duty cycle of each of said wavetrains is proportional to the corresponding frequency thereof and the pulses of said wavetrain are nonoverlapping with the pulses of other of said wavetrains.

Claim 23

A method as recited in claim 18 further comprising the step of smoothing in the composite waveform to provide an analog signal being proportionally equivalent to the binary number and equal to the product of the amplitude and the duty cycle of the composite waveform.

Claim 24

A method as recited in claim 18 further comprising the step of synchronizing the edges of the composite waveform with the least significant downcounting signal (N 0 ) to eliminate the effects of propagation delays.

Claim 25

A method as recited in claim 18 further comprising the step of referencing the composite waveform by setting a logic one level of the composite waveform to a precise reference voltage and a logic zero level of the composite waveform (CW) to a ground level.