High voltage power transistor circuits

Claim 2

A circuit arrangement comprising: a first high voltage bipolar power transistor, first control means for repeatedly cutting-off said first transistor, means connecting said first control means to a signal source which produces a drive signal for said first transistor, said first control means comprising a first device having an electric characteristic which is used to control said drive signal, a comparison stage having an output coupled to said first device for controlling the electric characteristic of said first device, first sensor means coupled to said first transistor for sensing the rate of change of base current of said first transistor each time said first transistor is cut off, first means for applying the sensing signa so produced to a first input of said comparison stage, second means for applying a time-related signal to a second input of the comparison stage, said first device controlling the instant of cut-off of said first transistor in response to a resulting comparison between said sensing signal and said time-related signal.

Claim 3

A circuit arrangement as claimed in claim 1, further comprising a second high voltage bipolar power transistor serially connected with said first transistor, second control means for repeatedly cutting off said second transistor, means connecting the second control means to said signal source for producing a drive signal for said second transistor, said second control means comprising a second device having an electric characteristic corresponding to that of said first device and which is used to control the drive signal for said second transistor, characterized in that said circuit arrangement additionally comprises second sensor means coupled to said second transistor for sensing the rate of change of base current of said second transistor each time said second transistor is cut-off thereby to derive a second sensing signal, and wherein said second means for applying applies the second sensing signal to said second input of said comparison stage as said time-related signal, said comparison stage comparing the phase relationship between said first and second sensing signals to produce the control for the electric characteristic of said first device to ensure that said first and second transistors are cut-off substantially simultaneously.

Claim 4

A circuit arrangement as claimed in claim 2, characterised in that said comparison stage additionally controls the electric characteristic of the second device.

Claim 5

A circuit arrangement as claimed in claim 2, characterized in that said first and second sensor means are each connected to a respective input of the comparison stage via a respective first and second pulse generator for producing a discrete pulse for said comparison stage each time its respective first and second transistor is cut-off.

Claim 6

A arrangement as claimed in claim 4, characterised in that each pulse generator is a gated monostable multivibrator that receives a gating signal from said signal source.

Claim 7

A circuit arrangement as claimed in claim 2 further comprising a line deflection coil and a serially connected capacitor of a video display device coupled across said first and second high voltage bipolar power transistors.

Claim 8

A circuit arrangement as claimed in claim 1, wherein said second means for applying applies pulses from said signal source to the second input of said comparison stage to form said time related signal.

Claim 9

A circuit arrangement as claimed in claim 7, further comprising a delay stage for coupling pulses from said signal source to the second input of said comparison stage.

Claim 10

A circuit arrangement as claimed in claim 8 wherein said first device controls the amplitude of drive signal applied to the base of said first power transistor thereby to control transistor charge carrier storage time.

Claim 11

A circuit arrangement as claimed in claim 9, characterised in that it additionally comprises means for sensing the power in said first high voltage bipolar power transistor, means for sensing when said power is at or near a minimum and for producing an output signal dependent on said power minimum, said output signal being applied to a control input of said delay stage which provides a variable delay for controlling its delay period.

Claim 12

A circuit arrangement as claimed in claim 2, characterized in that each said first and second device controls the amplitude of the drive signal applied to the base of its respective transistor to control charge carrier storage time for that transistor.

Claim 13

A circuit arrangement as claimed in claim 11, characterised in that the comparison stage controls the first device to substantially equalize the charge carrier storage times of the first and second transistors.

Claim 14

A circuit arrangement as claimed in claim 11, characterised in that each amplitude control device comprises a capacitor and a parallel resistive path, the resistive path in the first device comprising a further transistor whose conductivity is controlled by said comparison stage.

Claim 15

A circuit arrangement as claimed in claim 2 characterised in that each said first and second device is a delay device, the delay period of the first device being varied under the control of said comparison stage.

Claim 16

A circuit arrangement as claimed in claim 1 wherein the first sensor means is connected to a pulse generator which produces a discrete pulse for said comparison stage each time the first transistor is cut-off.

Claim 17

A circuit arrangement as claimed in claim 1 wherein said first device comprises a delay device having its delay period varied under control of said comparison stage.

Claim 18

A circuit arrangement as claimed in claim 1 wherein said first device controls the amplitude of drive signal applied to the base of the first power transistor thereby to control transistor charge carrier storage time, and wherein the first amplitude control device comprises a capacitor and a parallel resistive path, the resistive path in the first amplitude control device comprising a further transistor whose conductivity is controlled by said comparison stage.

Claim 19

A circuit arrangement as claimed in claim 1 wherein said first device controls the amplitude of drive signal applied to the base of said first power transistor thereby to control transistor charge carrier storage time.

Claim 20

A circut arrangement as claimed in claim 1 further comprising a line deflection coil of a video display device coupled to said first high voltage bipolar power transistor.