Transistor saturation control

Claim 1

A circuit arrangement for improving the characteristics of a transistor operated in saturation, comprising: first transistor means including first and second electrodes defining a first controllable current conducting path and also including a control electrode, said controllable current conducting path coupling a source of energizing potential with a load; conduction control means coupled to said control electrode of said first transistor means for establishing a control current therein for establishing the desired conductivity of said controlled current conducting path; second transistor means including first and second electrodes defining a second controllable current path and also including a control electrode, said second controllable current path being coupled to said first and control electrodes of said first transistor means for controlling said control current in said first transistor means; means coupling said control electrode of said second transistor means to said second electrode of said first transistor means thereby forming a degenerative feedback loop which reduces the effect of said conduction control means when said first transistor means is saturated; wherein: said first, second and control electrodes of said first and second transistor means comprise emitter, collector and base electrodes, respectively; said emitter electrode of said first transistor means is coupled to a first terminal of said source of energizing potential and said collector electrode is coupled to said load, said first transistor means being of PNP conductivity type; and said second transistor means comprises first and second compound-connected transistors of NPN conductivity type having effective emitter, collector and base electrodes corresponding to said first, second and control electrodes, respectively of said second transistor means.