Multiple port random access memory

Claim 2

A dual port memory unit comprising: two ports, each comprising busses for conveying control and data signals; a pair of memory cells, one memory cell of the memory unit corresponding to each port, each memory cell comprising means for storing a single data bit of one of first and second states, each memory cell being independently read and write accessed through the corresponding port; and means cross-coupling the memory cells so that when the state of a bit stored by one of the cells of the memory unit is changed when write accessed, the other cell of the memory unit changes the state of its stored bit following the write access of said one cell.

Claim 3

The dual port memory unit in accordance with claim 1 wherein said cross-coupling means comprises means for providing a cross-coupling signal of one of first and second states applied to each cell of said memory unit and for setting the state of said cross-coupling signal in accordance with the state of the memory cell being write accessed.

Claim 4

The dual port memory unit in accordance with claim 2 wherein each memory cell further comprises means for setting the state of its stored bit in accordance with the state of said cross-coupling signal when neither memory cell is being accessed.

Claim 5

The multiple port memory unit in accordance with claim 2 wherein said cross-coupling means includes current source means for providing a current to each of said cells, wherein said cross-coupling signal is set by diversion of said current by the cell being write accessed from the remaining cell.

Claim 6

A data storage unit for a multiple port memory, the data storage unit comprising a plurality of memory cells, each of said memory cells storing a separate data bit and being responsive to a corresponding one of a plurality of data signals, a corresponding one of a plurality of enable signals, and a common cross-coupling signal, each memory cell setting its stored data bit and said cross-coupling signal to states in accordance with a state of its corresponding data signal when its corresponding enable signal is asserted, each memory cell setting the state of its stored data bit in accordance with the state of said cross-coupling signal when the enable signal to each of said memory cells is deasserted.

Claim 7

A data storage unit for a multiple port memory, the data storage unit comprising a plurality of memory cells, each of said memory cells storing a separate data bit and being responsive to a corresponding one of a plurality of data signals, a corresponding one of a plurality of enable signals, and a common cross-coupling signal, each memory cell setting its stored data bit and said cross-coupling signal to states in accordance with a state of its corresponding data signal when its corresponding enable signal is asserted, each memory cell setting the state of its stored data bit in accordance with the state of said cross-coupling signal when the enable signal to each of said memory cells is deasserted.

Claim 8

A data storage unit for a multiple port memory comprising a plurality of memory cells, each memory cell responsive to a separate read/write enable signal, a separate corresponding data signal, and a common cross-coupling signal, each memory cell storing a data bit of state set in accordance with a state of its corresponding data signal while said read/write enable signal is asserted when said data signal is of one of first and second states, and set in accordance with a state of said cross-coupling signal when the separate read/write enable signals are deasserted and said cross-coupling signal is of one of said first and second states, each memory cell setting its corresponding data signal to one of said first and second states in accordance with the state of its stored data bit when said read/write enable signal is asserted while said data signal is of a third state, each memory cell driving said cross-coupling signal to one of said first and second states in accordance with the state of its stored data bit while said read/write enable signal is asserted.

Claim 9

A data storage unit for a multiple port memory comprising a plurality of memory cells, each memory cell responsive to a separate read/write enable signal, a separate corresponding data signal, and a common cross-coupling signal, each memory cell storing a data bit of state set in accordance with a state of its corresponding data signal while said read/write enable signal is asserted when said data signal is of one of first and second states, and set in accordance with a state of said cross-coupling signal when the separate read/write enable signals are deasserted and said cross-coupling signal is of one of said first and second states, each memory cell setting its corresponding data signal to one of said first and second states in accordance with the state of its stored data bit when said read/write enable signal is asserted while said data signal is of a third state, each memory cell driving said cross-coupling signal to one of said first and second states in accordance with the state of its stored data bit while said read/write enable signal is asserted.

Claim 10

The data storage unit in accordance with claim 6 wherein each of said memory cells comprises: first transistor means having a base, a collector, a first emitter and a second emitter; second transistor means having a base, a collector, a first emitter and a second emitter; first and second voltage clamps; and a circuit node, said separate read/write enable signal being applied to said circuit node, the collector of said first transistor means being coupled to the base of said second transistor means and coupled to said circuit node by said first voltage clamp, the collector of said second transistor means being coupled to the base of said first transistor means and coupled to said circuit node by said second voltage clamp, said separate data signal being applied across the first emitters of said first and second transistor means, and said cross-coupling signal being applied across the second emitters of said first and second transistor means.

Claim 11

A multiple port memory comprising: a plurality of ports, each comprising busses for conveying control and data signals; a plurality of memory units, each memory unit comprising a pair of memory cells, one memory cell of each memory unit corresponding to each port, each memory cell comprising means for storing a single data bit of one of first and second states, each memory cell being independently read and write accessed through the corresponding port; and means cross-coupling the memory cells of said each memory unit so that when the state of a bit stored by one of the cells of the memory unit is changed when write accessed, the other cell of the memory unit changes the state of its stored bit following the write access of said one cell.

Claim 12

A multiple port memory comprising: a plurality of ports, each comprising busses for conveying control and data signals; a plurality of memory units, each memory unit comprising a pair of memory cells, one memory cell of each memory unit corresponding to each port, each memory cell comprising means for storing a single data bit of one of first and second states, each memory cell being independently read and write accessed through the corresponding port; and means cross-coupling the memory cells of said each memory unit so that when the state of a bit stored by one of the cells of the memory unit is changed when write accessed, the other cell of the memory unit changes the state of its stored bit following the write access of said one cell.

Claim 13

The multiple port memory in accordance with claim 8 wherein said cross-coupling means provides a cross-coupling signal of one of first and second states applied to each cell of a memory unit and sets the state of said cross-coupling signal in accordance with the state of the memory cell being write accessed.

Claim 14

The multiple port memory in accordance with claim 9 wherein each memory cell of a memory unit further comprises means for setting the state of its stored bit in accordance with the state of said cross-coupling signal when no memory cell of a memory unit is being accessed.

Claim 15

The multiple port memory in accordance with claim 9 wherein said cross-coupling means includes current source means for providing a current to each of said cells, wherein said cross-coupling signal is set by diversion of said current by the cell being write accessed from the remaining cell.

Claim 16

A multiple port memory comprising: a plurality of data busses, one corresponding to each of a plurality of ports, each conveying a data bit; a plurality of address busses, one corresponding to each port, each conveying an address; a plurality of control lines, one corresponding to each port, each conveying a separate write control signal; a plurality of decoders, one corresponding to each port, each generating one of a separate set of output read/write enable signals in accordance with an address signal conveyed on a separate one of said address busses; a plurality of write control circuits, one corresponding to each port, each setting a state of a separate one of a plurality of data signals in accordance with a state of a data bit conveyed on a separate one of said data busses when a write control signal conveyed on a separate one of said write control lines is of a first state, and setting the state of said data bit on said separate one of said data busses in accordance with the state of said data signal when said write control signal is of a second state; a current source; and a plurality of memory units, each memory unit comprising a plurality of memory cells, one corresponding to each of said ports, each memory cell of a memory unit responsive to a separate one of said read/write enable signals, and a separate one of said data signals, first transistor means having a base, a collector, a first emitter and a second emitter, second transistor means having a base, a collector, a first emitter and a second emitter, first and second resistors, first and second diodes, and a circuit node, said read/write enable signal being applied to said circuit node, the collector of said first transistor means being coupled to the base of said second transistor and being coupled to said circuit node by said first resistor and by said first diode, the collector of said second transistor means being coupled to the base of said first transistor means and being coupled to said circuit node by said second resistor and by said second diode, the data signal being applied across the first emitters of said first and second transistor means, a third resistor coupling said current source to a second emitter of one of said first and second transistor means of each of said memory cells, and a fourth resistor coupling said current source to a second emitter of another of said first and second transistors of each of said memory cells.

Claim 17

A multiple port memory comprising: a plurality of data busses, one corresponding to each of a plurality of ports, each conveying a data bit; a plurality of address busses, one corresponding to each port, each conveying an address; a plurality of control lines, one corresponding to each port, each conveying a separate write control signal; a plurality of decoders, one corresponding to each port, each generating one of a separate set of output read/write enable signals in accordance with an address signal conveyed on a separate one of said address busses; a plurality of write control circuits, one corresponding to each port, each setting a state of a separate one of a plurality of data signals in accordance with a state of a data bit conveyed on a separate one of said data busses when a write control signal conveyed on a separate one of said write control lines is of a first state, and setting the state of said data bit on said separate one of said data busses in accordance with the state of said data signal when said write control signal is of a second state; a current source; and a plurality of memory units, each memory unit comprising a plurality of memory cells, one corresponding to each of said ports, each memory cell of a memory unit responsive to a separate one of said read/write enable signals, and a separate one of said data signals, first transistor means having a base, a collector, a first emitter and a second emitter, second transistor means having a base, a collector, a first emitter and a second emitter, first and second resistors, first and second diodes, and a circuit node, said read/write enable signal being applied to said circuit node, the collector of said first transistor means being coupled to the base of said second transistor and being coupled to said circuit node by said first resistor and by said first diode, the collector of said second transistor means being coupled to the base of said first transistor means and being coupled to said circuit node by said second resistor and by said second diode, the data signal being applied across the first emitters of said first and second transistor means, a third resistor coupling said current source to a second emitter of one of said first and second transistor means of each of said memory cells, and a fourth resistor coupling said current source to a second emitter of another of said first and second transistors of each of said memory cells.