Parallel processing state alignment

Claim 2

Circuitry in a multiple processor system for aligning the processing states of autonomous processors interconnected by a common communication channel, said circuitry comprising means for generating successive reference signals, means, responsive to the processors, for storing quantities indicative of the next processing states as scheduled by each of the associated processors, and means, coupled to said generating means and said storing means, for comparing the number of said generated reference signals to said quantities and for inhibiting said generating means whenever said number is equivalent to any of said quantities.

Claim 3

Circuitry as recited in claim 1 further comprising means, coupled to said storing means, for increasing said number of generated signals by a value corresponding to the earliest of said next processing states after a predetermined number of said successive reference signals has occurred.

Claim 4

In combination with a plurality of autonomous processing means communicating over a common bus, circuitry characterized by means for generating reference signals at a prescribed rate, and in association with each processing means, state alignment means comprising means, coupled to its associated processing means, for storing a quantity indicative of the next event as scheduled by the associated processing means, means, responsive to said means for generating, for registering said reference signals, means, coupled to said storing means and said registering means, for comparing the contents of said storing means to the contents of said registering means to provide a comparison signal whenever said contents are equivalent, and means, coupled to said comparing means, for inhibiting said means for generating whenever said comparison signal is present and for notifying the associated processing means upon detection of said comparison signal.

Claim 5

In combination with a plurality of autonomous processing means communicating over a common bus, circuitry characterized by means for generating reference signals at a prescribed rate, and in association with each processing means, state alignment means comprising means, coupled to its associated processing means, for storing a quantity indicative of the next event as scheduled by the associated processing means, means, responsive to said means for generating, for registering said reference signals, means, coupled to said storing means and said registering means, for comparing the contents of said storing means to the contents of said registering means to provide a comparison signal whenever said contents are equivalent, and means, coupled to said comparing means, for inhibiting said means for generating whenever said comparison signal is present and for notifying the associated processing means upon detection of said comparison signal.

Claim 6

The circuitry as recited in claim 3 wherein said means for notifying includes means for notifying all other processing means upon detection of said comparison signal.

Claim 7

The circuitry as recited in claim 3 wherein said circuitry further comprises means, coupled to the plurality of each said storing means and each said registering means, for loading the contents of said storing means having the least-valued quantity into each said register means if said comparison signal is not generated by any of said comparing means before a preselected number of said reference signals.

Claim 8

The circuitry as recited in claim 3 wherein said alignment means further comprises rapid advance means, and said circuitry further comprises a data bus interconnecting the plurality of said rapid advance means.

Claim 9

The circuitry as recited in claim 6 wherein said rapid advance means further comprises means, responsive to said generating means, for providing a strobe signal after a predetermined number of said reference signals, means, coupled to said storing means, for receiving the contents of said storing means after said comparison signal is removed, means, interposed between said receiving means and said data bus, for serially placing at said rate the contents of said receiving means onto said data bus until the occurrence of a mismatch between said contents of said receiving means and data on said data bus, means, coupled to said registering means, for saving the data generated on said data bus and then loading the contents of said saving means into said register means whenever said strobe signal is produced, and means for reinitializing each said rapid advance means if any of said alignment means produces said comparison signal before the occurrence of said strobe signal.

Claim 10

In combination with at least two stand-alone processors interconnected with a common communication bus, circuitry comprising master clock means for providing gated clock signals, and a plurality of alignment means, one for each of the processors, each said alignment means comprising means, coupled to its associated processor, for storing the time of the next event as scheduled by the associated processor, means, responsive to said clock means, for registering said gated clock signals, means, coupled to said means for storing and said means for registering, for generating a disable signal whenever the contents of said means for storing and said means for registering are equal and for generating an enable signal otherwise, and means, coupled to said means for generating and said clock means, for inhibiting said clock means and for notifying all processors in response to said disable signal and for enabling said clock means in response to said enable signal.

Claim 11

In combination with at least two stand-alone processors interconnected with a common communication bus, circuitry comprising master clock means for providing gated clock signals, and a plurality of alignment means, one for each of the processors, each said alignment means comprising means, coupled to its associated processor, for storing the time of the next event as scheduled by the associated processor, means, responsive to said clock means, for registering said gated clock signals, means, coupled to said means for storing and said means for registering, for generating a disable signal whenever the contents of said means for storing and said means for registering are equal and for generating an enable signal otherwise, and means, coupled to said means for generating and said clock means, for inhibiting said clock means and for notifying all processors in response to said disable signal and for enabling said clock means in response to said enable signal.

Claim 12

The circuitry as recited in claim 8 wherein said alignment means further comprises rapid advance means, and said circuitry further comprises a data bus linking each said rapid advance means.

Claim 13

The circuitry as recited in claim 9 wherein said rapid advance means further comprises counter means, responsive to said clock means, for generating a strobe signal after a preselected number of said gated clock signals, buffer means, coupled to said storing means, for receiving the contents of said storing means in a parallel mode whenever said enable signal is generated, least-value determining means, coupled between said buffer means and said data bus, for serially transmitting at the rate of said clock means the contents of said buffer means over said data bus until a mismatch occurs between said contents of said buffer means and the data on said data bus, advance register means, coupled to said means for registering, for saving the data generated by said data bus and then parallel loading of the contents of said advance register means into said means for registering whenever said strobe signal occurs, and means, coupled to said advance register means, said counter means, said buffer means and said determining means for resetting each said rapid advance means whenever any of said alignment means produces said disable signal before the occurrence of said strobe signal.

Claim 16

The method as recited in claim 11 further comprising the step of increasing said number of pulses by a value corresponding to the earliest of said next processing states after a predetermined number of said pulses has elapsed.