Abstract A process for the fabrication of shallow p + and n + doped layers suitable for the sources and drains of submicron CMOS transistors comprises applying a layer of polysilicon (1) over a gate oxide layer (2) which is surrounded by a field oxide isolation layer (3) located on a suitable substrate (4) and applying a resist layer (5) to the polysilicon layer in a selected region of the polysilicon layer overlying the gate oxide to define a gate electrode. Selective ion implantation then takes place to form the source and drain regions (6, 7), the implementation extending through the oxide layer to a limited extent except in the region masked by the resist layer. The polysilicon layer and resist layer are then etched away to leave a gate electrode (8) extending from the oxide layer (2) and the source and drain regions are then activated and difussed to ˜0.1 μm junction depth. The oxide is then removed in said source and drain regions and a silicide or other conductive layer (10) is then applied to reduce the sheet resistance to ˜8Ω/ or less.
A process for the production of a transistor which comprises applying a layer of polysilicon over a gate oxide layer which is surrounded by a field oxide isolation layer located on a suitable substrate; applying a resist layer to the polysilicon layer in a selected region of the latter overlying the gate oxide to define a gate electrode; selective ion implantation to form source and drain regions, said implantation extending through the gate oxide layer to a limited extent except in the region masked by said resist layer; etching away the polysilicon layer and resist layer to leave a gate electrode extending from said oxide layer, activating the source and drain regions and removing the gate oxide in said regions; and finally depositing a conductive layer on the said gate electrode and source and drain regions.
Claim 2
Dependent Claim
136 words
A process for the production of a transistor which comprises applying a layer of polysilicon over a gate oxide layer which is surrounded by a field oxide isolation layer located on a suitable substrate; applying a resist layer to the polysilicon layer in a selected region of the latter overlying the gate oxide to define a gate electrode; selective ion implantation to form source and drain regions, said implantation extending through the gate oxide layer to a limited extent except in the region masked by said resist layer; etching away the polysilicon layer and resist layer to leave a gate electrode extending from said oxide layer, activating the source and drain regions and removing the gate oxide in said regions; and finally depositing a conductive layer on the said gate electrode and source and drain regions.
Claim 3
Dependent Claim
22 words
A process according to claim 1, wherein the source and drain regions are activated after the polysilicon layer has been etched away.
Claim 4
Dependent Claim
24 words
A process according to claim 2, wherein the source and drain regions are activated after the oxide layer has been removed from these regions.
Claim 5
Dependent Claim
16 words
A process according to any preceding claim 1, wherein the said conductive layer comprises a silicide.
Claim 6
Dependent Claim
17 words
A process according to claim 1 wherein the said conductive layer comprises a selective refractory metal deposition.
Claim 7
Dependent Claim
22 words
A process according to claim 1, wherein the gate is provided with oxide fillets prior to the deposition of said conductive layer.