Patent US4831518A successfully refreshed from Google Patents.
US4831518A
Expired / Lapsed
US
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Multiprocessor interrupt rerouting mechanism
Assignee: Bull HN Information Systems Inc
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Filing: 1986-08-26
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Granted: 1989-05-16
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Expires: 2006-08-26
Abstract
Abstract A multiprocessor interrupt rerouting mechanism and method is disclosed for rerouting messages intended for a first processor to a second processor. In a fault tolerant computer system having several processors or LANs under the control of a single controller, when the controller completes a communication task requested by one of the processors, it will send an interrupt request to the requesting processor which then notifies the application process for which the communication task was performed, information regarding the status of the communication task. If for any reason the requesting processor being interrupted is inoperative or too busy to handle the interrupt request, the application process is then notified as to the status of the communication task by rerouting the interrupt request from the controller so that another processor can handle it.
Inventors
- 👤 Kin C. Yu
- 👤 Allen C. Hirtle
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 21:21
CPC Classifications
H; H04; H04L; H04L5/00; G; G06; G06F; G06F9/00; G06F9/06; G06F9/46; G06F9/48; G06F9/4806; G06F9/4812; H04L12/00; H04L12/28; H04L12/46; H04L12/4604; H04L12/462; H04L12/4625; H04L69/00; G06F11/00; G06F11/07; G06F11/16; G06F11/20; H04L69/30; H04L69/32; H04L69/321
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
375 words
In a local area network (LAN) system having a computer system comprised of at least one bus, a plurality of CPUs coupled to said bus for executing application processes, each CPU having a memory associated to it, said LAN also having at least one controller coupled to said bus and including at least one controller memory, said LAN system further including resources coupled to said bus, and additional LANs coupled to said at least one controller, and means for creating LAN control blocks (LCBs) within any of said memories, said LCBs for providing control information to effect the transfer of messages to/from said memories, resources, controller and LANs, said controller capable of effecting the interruption of any of said CPUs, a multiprocessor interrupt rerouting mechanism for retouring messages intended for any one of said plurality of said processors to a different one of said plurality of said processors; (a) first means for requesting communication service form said controller on behalf of a first process executing on any one of said plurality of CPUs wherein said controller is interrupted by said any one of said plurality of said CPUs; (b) second means in said controller for creating queues of LCBs for said any one of said processors, when said controller cannot immediately service a request for communication service; (c) third means in said controller for interrupting said any one of said plurality of said CPUs to provide a status message to said first process executing on said any one of said plurality of said CPUs; and, (d) fourth means in said controller for rerouting said status message to said first process by interrupting a different one of said plurality of said CPUs to provide the status message to said first process, whereby when said any one of said plurality of said CPUs is unable to receive an interrupt from said controller and notify said first process of the status of its request, said first process is notified via an alternate route through a different one of said plurality of said CPUs; and, (e) fifth means for creating a rerouting table in the controller memory for each queue created by said controller when any one of said plurality of said CPUs is unable to receive an interrupt.
Claim 2
Dependent Claim
375 words
In a local area network (LAN) system having a computer system comprised of at least one bus, a plurality of CPUs coupled to said bus for executing application processes, each CPU having a memory associated to it, said LAN also having at least one controller coupled to said bus and including at least one controller memory, said LAN system further including resources coupled to said bus, and additional LANs coupled to said at least one controller, and means for creating LAN control blocks (LCBs) within any of said memories, said LCBs for providing control information to effect the transfer of messages to/from said memories, resources, controller and LANs, said controller capable of effecting the interruption of any of said CPUs, a multiprocessor interrupt rerouting mechanism for retouring messages intended for any one of said plurality of said processors to a different one of said plurality of said processors; (a) first means for requesting communication service form said controller on behalf of a first process executing on any one of said plurality of CPUs wherein said controller is interrupted by said any one of said plurality of said CPUs; (b) second means in said controller for creating queues of LCBs for said any one of said processors, when said controller cannot immediately service a request for communication service; (c) third means in said controller for interrupting said any one of said plurality of said CPUs to provide a status message to said first process executing on said any one of said plurality of said CPUs; and, (d) fourth means in said controller for rerouting said status message to said first process by interrupting a different one of said plurality of said CPUs to provide the status message to said first process, whereby when said any one of said plurality of said CPUs is unable to receive an interrupt from said controller and notify said first process of the status of its request, said first process is notified via an alternate route through a different one of said plurality of said CPUs; and, (e) fifth means for creating a rerouting table in the controller memory for each queue created by said controller when any one of said plurality of said CPUs is unable to receive an interrupt.
Claim 3
Dependent Claim
67 words
The LAN system as recited in claim 1 wherein said rerouting table is characterized in that it is accessed by said controller by a queue number and the contents of the table comprise a CPU address which is utilized to interrupt said any of said plurality of said CPUs in order to provide status information to application processes executing on said any of said plurality of CPUs.
Claim 4
Dependent Claim
48 words
The LAN system as recited in claim 2 including sixth means in said controller for determining when any of said CPUs does not accept an interrupt request from said controller, because said any of said plurality of CPUs being sent an interrupt request is either inoperative or overloaded.
Claim 5
Dependent Claim
61 words
The LAN system as recited in claim 3 including seventh means coupled to said sixth means for substituting a different CPU address for the address of said any of said plurality of CPUs in the queue of said any of said plurality of CPUs maintained by said controller, when said any of said plurality of said CPUs becomes inoperative or overloaded.
Claim 6
Dependent Claim
26 words
The LAN system as recited in claim 4 including eighth means coupled to said seventh means for storing said different CPU address in a predetermined format.
Claim 7
Dependent Claim
58 words
The LAN system as recited in claim 5 wherein said eighth means is characterized in that it includes a CPU number which will be substituted for the address of said any of said plurality of CPUs, and a queue number of a queue maintained by said controller of pending interrupts for said any of said plurality of CPUs.
Claim 8
Dependent Claim
360 words
In a local area network (LAN) system having a computer system comprising a at least one bus, at least a first CPU and a second CPU coupled to said bus for executing first and second processes respectively thereon, each of said first and second CPUs having first and second memories respectively coupled to said bus, said computer system also including resources coupled to said bus, and further including a controller coupled to said bus, said controller including a controller memory and being capable of interrupting said first and second CPUs, a multiprocessor interrupt rerouting mechanism for rerouting by said controller first messages intended to be delivered by said first CPU to said first process so that the said first messages are delivered to said first process by said second CPU comprising: (a) first means for requesting service by said first process from said controller by interrupting said controller by said first CPU; (b) second means in said controller for requesting service by said second process from said controller by interrupting said controller by said second CPU; (c) third means in said controller for creating first and second queues of interrupt messages for said first and second CPUs respectively, when said controller cannot immediately service said first or second processes; (d) fourth means in said controller for interrupting said first CPU to provide a first status message from said first queue to said first process executing on said first CPU; and, (e) fifth means in said controller for rerouting said first status message to said first process by interrupting said second CPU to deliver said first status message t said first process, whereby when said first CPU is disabled or overloaded and cannot receive a first status message to relay to said first process, said second CPU is interrupted by said controller and said first status message is delivered to said first process by said second CPU and; (f) sixth means in said controller for creating a rerouting table in the controller memory for said first and second queues of interrupt messages, when said first CPU is disabled or cannot receive said first status message to relay to said first process.
Claim 9
Dependent Claim
360 words
In a local area network (LAN) system having a computer system comprising a at least one bus, at least a first CPU and a second CPU coupled to said bus for executing first and second processes respectively thereon, each of said first and second CPUs having first and second memories respectively coupled to said bus, said computer system also including resources coupled to said bus, and further including a controller coupled to said bus, said controller including a controller memory and being capable of interrupting said first and second CPUs, a multiprocessor interrupt rerouting mechanism for rerouting by said controller first messages intended to be delivered by said first CPU to said first process so that the said first messages are delivered to said first process by said second CPU comprising: (a) first means for requesting service by said first process from said controller by interrupting said controller by said first CPU; (b) second means in said controller for requesting service by said second process from said controller by interrupting said controller by said second CPU; (c) third means in said controller for creating first and second queues of interrupt messages for said first and second CPUs respectively, when said controller cannot immediately service said first or second processes; (d) fourth means in said controller for interrupting said first CPU to provide a first status message from said first queue to said first process executing on said first CPU; and, (e) fifth means in said controller for rerouting said first status message to said first process by interrupting said second CPU to deliver said first status message t said first process, whereby when said first CPU is disabled or overloaded and cannot receive a first status message to relay to said first process, said second CPU is interrupted by said controller and said first status message is delivered to said first process by said second CPU and; (f) sixth means in said controller for creating a rerouting table in the controller memory for said first and second queues of interrupt messages, when said first CPU is disabled or cannot receive said first status message to relay to said first process.
Claim 10
Dependent Claim
74 words
The computer system as recited in claim 7 wherein said rerouting table is characterized in that it is resident in said controller memory and having a predetermined format and is accessed by said controller by a queue number, and the contents of said table comprise a first CPU address which is utilized by said controller to interrupt said first CPU in order that it can provide said first status message to said first process.
Claim 11
Dependent Claim
38 words
The computer system as recited in claim 8 including seventh means in said controller for determining when said first CPU does not accept an interrupt request from said controller, because said first CPU is either inoperative or overloaded.
Claim 12
Dependent Claim
45 words
The computer system as recited in claim 9 including eighth means coupled to said seventh means for substituting a second CPU address for the address of said first CPU in said first queue when said controller determines that said first CPU is inoperative or overloaded.
Claim 13
Dependent Claim
22 words
The computer system as recited in claim 10 including ninth means coupled to said eighth means for storing said second CPU address.
Claim 14
Dependent Claim
27 words
The computer system as recited in claim 11 wherein said ninth means are characterized in that it includes a second CPU number and a second queue number.
Claim 15
Dependent Claim
21 words
The computer system as recited in claim 12 including a plurality of local area network systems (LANs) coupled to said controller.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-05-15 | 1992-11-14 | 1993-05-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-05-15 | 1996-11-14 | 1997-05-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-05-15 | 2000-11-14 | 2001-05-16 | $7700.00 | Window Closed / Lapsed |