Abnormality detection alarm circuit for output circuit

Claim 1

An abnormality detection alarm circuit for an output transistor for driving a load, comprising: (a) a short detection circuit, connected between a base terminal and an emitter terminal of the output transistor, for detecting a shorted load and generating a short detection signal; (b) an open detection circuit, connected in parallel to said short detection circuit, for detecting an open load and generating an open detection signal; (c) a delay start circuit, connected to said short detection circuit and said open detection circuit, for generating a delay start signal in response to any one of the short detection signal and the open detection signal; (d) a delay circuit, connected to said delay start circuit, for generating a delayed short signal after said short detection circuit has kept generating the short detection signal beyond a predetermined time during which the output transistor is operating in a stable operation range and a delayed open signal after said open detection circuit has kept generating the open detection signal beyond the predetermined time; (e) a latch circuit connected to said delay circuit, for generating a first voltage level signal in response to absence of the delayed short signal and the delayed open signal and a second voltage level signal in response to the presence of any one of the delayed short signal and the delayed open signal; (f) an output transistor driving circuit, connected to said latch circuit and between the base and a collector of the output transistor, for turning off the output transistor when said latch circuit generates the second voltage level signal; and (g) an alarm circuit, connected to said latch circuit, for generating an alarm signal in response to the second voltage level signal.