Patent US4831338A successfully refreshed from Google Patents.
US4831338A
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Synchronizing clock signal generator
Assignee: Individual
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Filing: 1988-05-11
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Granted: 1989-05-16
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Expires: 2008-05-11
Abstract
Abstract A synchronizing clock signal generator has, in combination with a PLL circuit, a signal delay circuit for delaying a reference input signal by a prescribed time and issuing a reference signal, and a shift register receptive of the reference input signal and a clock signal which is an oscillation signal from a voltage-controlled oscillator or a signal produced by frequency-dividing the oscillation signal by an integer, for issuing a comparison signal in synchronism with the clock signal. The comparison signal and the reference signal are compared in phase. Even if the reference input signal is not a pulse signal of a fixed frequency, a synchronizing clock signal can be reproduced, insofar as the reference input signal is a pulse signal with its polarity inverted at the time of a multiple of a prescribed natural period.
Inventors
- 👤 Noboru Yamaguchi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 22:43
CPC Classifications
H; H04; H04L; H04L7/00; H04L7/02; H04L7/033
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
203 words
A synchronizing clock signal generator comprising: (i) a signal delay circuit for delaying a reference input signal by a prescribed time and issuing a reference signal; (ii) a phase comparator receptive of said reference signal and a comparison signal for issuing a signal representative of the difference in phase or frequency between said reference signal and said comparison signal; (iii) a low-pass filter for smoothing the signal applied thereto from said phase comparator; (iv) a voltage-controlled oscillator for issuing an oscillation signal with an oscillation frequency thereof being controlled by an output voltage from said low-pass filter; and (v) a shift register receptive of said reference input signal and a clock signal which is said oscillation signal or a signal produced by frequency-dividing said oscillation signal by an integer, for issuing said comparison signal in synchronism with said clock signal, the arrangement being such that when a pulse signal with its polarity inverted at the time of a multiple of a prescribed natural period is applied as said reference input signal, said clock signal is produced in synchronism with said reference input signal, said clock signal having a period equal to said natural period or said natural period as divided by an integer.
Claim 2
Dependent Claim
203 words
A synchronizing clock signal generator comprising: (i) a signal delay circuit for delaying a reference input signal by a prescribed time and issuing a reference signal; (ii) a phase comparator receptive of said reference signal and a comparison signal for issuing a signal representative of the difference in phase or frequency between said reference signal and said comparison signal; (iii) a low-pass filter for smoothing the signal applied thereto from said phase comparator; (iv) a voltage-controlled oscillator for issuing an oscillation signal with an oscillation frequency thereof being controlled by an output voltage from said low-pass filter; and (v) a shift register receptive of said reference input signal and a clock signal which is said oscillation signal or a signal produced by frequency-dividing said oscillation signal by an integer, for issuing said comparison signal in synchronism with said clock signal, the arrangement being such that when a pulse signal with its polarity inverted at the time of a multiple of a prescribed natural period is applied as said reference input signal, said clock signal is produced in synchronism with said reference input signal, said clock signal having a period equal to said natural period or said natural period as divided by an integer.
Claim 3
Dependent Claim
82 words
A synchronizing clock signal generator according to claim 1, wherein said signal delay circuit has a delay time τ in the range of: (n-0.75)T+TA<τ<(n-0.25)T+TA (4) where T is one period of said clock signal applied to said shift register, TA is a response delay time of the signal issued from said shift register with respect to a positive-going edge or a negative-going edge serving as a clock of said clock signal, and n is the shift bit number of said shift register.
References Cited (Backward Citations)
US4698601A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-05-15 | 1992-11-14 | 1993-05-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-05-15 | 1996-11-14 | 1997-05-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-05-15 | 2000-11-14 | 2001-05-16 | $7700.00 | Window Closed / Lapsed |