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US4829824A
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Method for digital peak value measurement for ultrasonic test pulses
Assignee: Deutsches Zentrum für Luft- und Raumfahrt eV
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Filing: 1988-03-02
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Granted: 1989-05-16
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Expires: 2008-03-02
Abstract
Abstract Method for the digital peak value measurement for ultrasonic test pulses having a predetermined pulse repetition frequency. After amplification, the input signal to be measured is present at a comparator circuit the output of which is connected, within a predetermined time slot, periodically generated, for the expected signal time range, to a memory which is reset at the beginning of the time slot. The received signal is applied to a window comparator the window width of which corresponds to one voltage step of a reference voltage which is supplied by a D/A converter and which can be changed in steps. The D/A converter is controlled by a digital counter the direction of counting of which is controlled in dependence on the memory contents and which is stopped in the case of equality between the received signal within the time slot and the respective reference voltage. The display is derived from the final count. The clock signal for the digital counter has the same frequency as the time slot and is derived from it. To extend the dynamic range, the amplified signal can be applied to the window comparator with different signal levels.
Inventors
- 👤 Wolfgang Hillger
- 👤 Jurgen D. E. Klebusch
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 07:34
CPC Classifications
G; G01; G01H; G01H1/00; G01H1/12; G01H1/16; G01R; G01R19/00; G01R19/04; Y; Y10; Y10S; Y10S73/00; Y10S73/901
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
266 words
A method for measuring digital peak values of ultrasonic test pulses which comprises: operating within a high dynamic range with a predetermined pulse repetition frequency; applying, after linear amplification, a received signal to a measuring circuit having a window comparator circuit with two comparators; supplying a reference voltage stepwise by means of a D/A-converter to the window comparator circuit; forming a window with the two comparators, the window having a window width within a range of 105 to 110% of one voltage step of the stepwise reference voltage; periodically generating for an expected signal range a predetermined time slot; connecting the output of the window comparator to a memory means during the predetermined time slot, the memory means having bistable memory units for connecting each output of the two comparators; resetting the memory means at the beginning of the predetermined time slot; driving the D/A-converter with a digital counter which is clocked with a clock signal having the same frequency as the predetermined time slot, wherein the clock signal being derived from the predetermined time slot; controlling the direction of counting of the digital counter with the actual status of the bistable memory units connected to each of the comparators by setting the respective bistable memory unit if the comparators are triggered, and stopping the digital counter if the voltage of a peak value of the received signal is within the window formed by the two comparators; and processing a digital signal of a final count from the digital counter to provide a data output representing the measured digital peak value of the ultrasonic test pulses.
Claim 2
Independent Claim
266 words
A method for measuring digital peak values of ultrasonic test pulses which comprises: operating within a high dynamic range with a predetermined pulse repetition frequency; applying, after linear amplification, a received signal to a measuring circuit having a window comparator circuit with two comparators; supplying a reference voltage stepwise by means of a D/A-converter to the window comparator circuit; forming a window with the two comparators, the window having a window width within a range of 105 to 110% of one voltage step of the stepwise reference voltage; periodically generating for an expected signal range a predetermined time slot; connecting the output of the window comparator to a memory means during the predetermined time slot, the memory means having bistable memory units for connecting each output of the two comparators; resetting the memory means at the beginning of the predetermined time slot; driving the D/A-converter with a digital counter which is clocked with a clock signal having the same frequency as the predetermined time slot, wherein the clock signal being derived from the predetermined time slot; controlling the direction of counting of the digital counter with the actual status of the bistable memory units connected to each of the comparators by setting the respective bistable memory unit if the comparators are triggered, and stopping the digital counter if the voltage of a peak value of the received signal is within the window formed by the two comparators; and processing a digital signal of a final count from the digital counter to provide a data output representing the measured digital peak value of the ultrasonic test pulses.
Claim 3
Dependent Claim
19 words
A method as claimed in claim 1, wherein a logarithmic D/A converter is used for generating the reference voltage.
Claim 4
Dependent Claim
27 words
A method as claimed in claim 1, wherein the digital signal of the digital counter is transferred to a second D/A converter for providing analog data output
Claim 5
Dependent Claim
26 words
A method as claimed in claim 1, wherein the received amplified signal is applicable to the window comparator circuit with at least two different signal levels.
Claim 6
Dependent Claim
19 words
A method as claimed in claim 4, wherein the different signal levels are generated by means of voltage dividers.
Claim 7
Dependent Claim
24 words
A method as claimed in claim 4, wherein the received signal is initially applied to a plurality of parallel amplifiers with different gain factors.
Claim 8
Dependent Claim
40 words
A method as claimed in claim 1, wherein the counter is stopped at its highest or lowest step in the case of signal voltages which are above or below the dynamic range, and an above- or below-range indication is triggered.
Claim 9
Dependent Claim
131 words
A method as claimed in claim 1, wherein the received signal may be associated with one of at least two different signal rangers, each of which is associated with an equal part of the total number of reference voltage steps of the whole dynamic range, which parts correspond to the total number of reference voltage steps divided by the number of different signal levels, and wherein the received signal associated with each of its different signal ranges is applied to a separate measuring circuit and the outputs of the digital counter of each of the measuring circuits are connected to a processing circuit, in which the final count is multiplied by a factor depending on the signal level applied to the measuring circuit by which the final count has been issued.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-05-15 | 1992-11-14 | 1993-05-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-05-15 | 1996-11-14 | 1997-05-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-05-15 | 2000-11-14 | 2001-05-16 | $7700.00 | Window Closed / Lapsed |