Defective element disabling circuit having a laser-blown fuse

Claim 1

A row decoder circuit for use in a semiconductive memory comprising an array of storage elements arranged in rows and columns and including redundant rows comprising: a NAND gate, including a plurality of input terminals, said NAND gate comprising a plurality of N-channel transistors having their drain-source paths connected in series between ground and a first node and an equal number of P-channel transistors having their drain-source paths connected in parallel between a point of high voltage and a second node, the gate electrode of each N-channel transistor being connected to a gate electrode of a respective P-type transistor and to a separate one of said input terminals, a fuse element that is blown open when there is a defective element in the row associated with the decoder circuit having a first terminal connected to said first node and a second terminal connected to said second node, a pull up P-channel transistor having its drain-source path connected between the point of high voltage and said second node and its gate electrode connected to ground, and an inverter having its input connected only to said second node and its output connected only to an output node to be controlled, and characterized in that the current-carrying capacity of the pull-up transistor is small compared to the current-carrying capacity of the current path through the NAND circuit to ground whereby the output node provides a low impedance independent of the state of the fuse.