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Patent US4829463A successfully refreshed from Google Patents.
US4829463A
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US
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Programmed time-changing coefficient digital filter
Assignee: AKAI MUSICAL INSTRUMENT Corp
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Filing: 1986-03-26
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Granted: 1989-05-09
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Expires: 2006-03-26
Abstract
Abstract A time-changing coefficient digital filter having a data RAM for storing input data, a purality of N data registers at the output of the data RAM forming a delay element, a coefficient RAM storing coefficient values, coefficient registers temporarily storing respective coefficients, and a multiplier for multiplying data read out of data registers and coefficient registers respectively. Data from the multiplier and inputs is accumulated in an adder. Coefficient registers and data registers are updated by data from the data RAM and coefficient RAM. The coefficient digital filter provides a sum of products sequentially read out of the coefficient and data registers. The digital filter is applied to produce a musical instrumet having improved tonal qualities.
Inventors
- 👤 Masahiro Kakishita
- 👤 Hiroshi Katsumoto
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 23:03
CPC Classifications
H; H03; H03H; H03H17/00; H03H17/02; H03H17/0294; H03H17/04; Y; Y10; Y10S; Y10S84/00; Y10S84/09
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
219 words
A programmed time-changing coefficient digital filter comprising; data storing RAM means for temporarily storing input data; a plurality of N data registers connected to the output of said data storing RAM means forming a delay means; coefficient RAM storage means for storing coefficients; a plurality of 2 N coefficient registers for temporarily storing respective coefficients; coefficient control means for updating said plurality of 2 N coefficient registers by replacing coefficient values stored in said plurality of 2 N coefficient registers with coefficient values from said coefficient RAM means; multiplying means for multiplying delayed data and coefficients read out from said data registers and coefficient registers respectively; adder means receiving the output of said multiplying means for accumulating output data from said multiplying means and input data; means in said coefficient control means for replacing the coefficient values in said plurality of 2 N coefficient registers with coefficient values from said coefficient RAM means when signal processing time is a predetermined value; transfer means for transferring data between said plurality of N data registers and said data RAM to update delayed data in said data register; whereby a sum of the products of coefficients sequentially read out of said plurality of 2 N coefficient registers and delayed data sequentially read out of said plurality of N data registers is provided.
Claim 2
Dependent Claim
219 words
A programmed time-changing coefficient digital filter comprising; data storing RAM means for temporarily storing input data; a plurality of N data registers connected to the output of said data storing RAM means forming a delay means; coefficient RAM storage means for storing coefficients; a plurality of 2 N coefficient registers for temporarily storing respective coefficients; coefficient control means for updating said plurality of 2 N coefficient registers by replacing coefficient values stored in said plurality of 2 N coefficient registers with coefficient values from said coefficient RAM means; multiplying means for multiplying delayed data and coefficients read out from said data registers and coefficient registers respectively; adder means receiving the output of said multiplying means for accumulating output data from said multiplying means and input data; means in said coefficient control means for replacing the coefficient values in said plurality of 2 N coefficient registers with coefficient values from said coefficient RAM means when signal processing time is a predetermined value; transfer means for transferring data between said plurality of N data registers and said data RAM to update delayed data in said data register; whereby a sum of the products of coefficients sequentially read out of said plurality of 2 N coefficient registers and delayed data sequentially read out of said plurality of N data registers is provided.
Claim 3
Dependent Claim
28 words
The coefficient filter according to claim 1 including external coefficient replacing means connected to said coefficient RAM means for selectively replacing coefficient values in said coefficient RAM means.
Claim 4
Dependent Claim
19 words
The coefficient filter according to claim 2 in which said external replacing means comprises a programmable computer processing unit.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-05-08 | 1992-11-07 | 1993-05-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-05-08 | 1996-11-07 | 1997-05-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-05-08 | 2000-11-07 | 2001-05-09 | $7700.00 | Window Closed / Lapsed |