Synchronizing signal generating circuit

Claim 2

A synchronizing signal generating circuit comprising: equalizing pulse remover means for receiving a composite synchronizing signal as an input signal, said equalizing pulse remover means being adapted to be coupled to a reference input terminal of a frequency synthesizer; and an F/V converter for controlling said equalizing pulse remover means, said F/V converter being receptive of said composite synchronizing signal as an input signal.

Claim 3

A synchronizing signal generating circuit according to claim 1, wherein said F/V converter receives a video synchronizing signal as the input signal and comprises a pulse shaper and a low-pass filter connected thereto, said equalizing pulse remover means being controlled by an output signal from said low-pass filter.

Claim 4

A synchronizing signal generating circuit comprising equalizing pulse remover means for receiving a composite synchronizing signal as an input signal, said equalizing pulse remover means being adapted to be coupled to a reference input terminal of a frequency synthesizer including at least a prescaler; and an F/V converter for producing as an output signal thereof a control signal for controlling said equalizing pulse remover means, said F/V converter being receptive of said composite synchronizing signal as an input signal.

Claim 5

A synchronizing signal generating circuit comprising equalizing pulse remover means for receiving a composite synchronizing signal as an input signal, said equalizing pulse remover means being adapted to be coupled to a reference input terminal of a frequency synthesizer including at least a prescaler; and an F/V converter for producing as an output signal thereof a control signal for controlling said equalizing pulse remover means, said F/V converter being receptive of said composite synchronizing signal as an input signal.

Claim 6

A synchronizing signal generating circuit according to claim 3, wherein said F/V converter comprises a pulse shaper and a low-pass filter connected thereto, said equalizing pulse remover means and/or said prescaler being controlled by an output signal from said low-pass filter.

Claim 7

A synchronizing signal generating circuit comprising: a field discriminating circuit for deriving a field discriminating signal from a composite synchronizing signal relative to a plurality of composite video signals having different numbers of scanning lines and produced from different video output devices; an F/V converter; an equalizing pulse remover and a vertical synchronizing signal separator which are controlled by said F/V converter, said F/V converter, said equalizing pulse remover, and said vertical synchronizing signal separator being receptive of the composite synchronizing signal; and a field detector including at least one delay flip-flop means and having a data input terminal connected to an output terminal of said equalizing pulse remover, a trigger input terminal connected to an output terminal of said vertical synchronizing signal separator, and a time constant control terminal connected to an output terminal of said F/V converter; said field discriminating circuit being arranged such that at a time or during a time period upon elapse of a time period from a prescribed leading edge of a rectangular-wave output signal from said vertical synchronizing signal separator, said field detector determines the binary level of an output signal applied by said equalizing pulse remover to said data input terminal for deriving the field discriminating signal of either a high level or a low level.

Claim 8

A synchronizing signal generating circuit comprising: a field discriminating circuit for deriving a field discriminating signal from a composite synchronizing signal relative to a plurality of composite video signals having different numbers of scanning lines and produced from different video output devices; an F/V converter; an equalizing pulse remover and a vertical synchronizing signal separator which are controlled by said F/V converter, said F/V converter, said equalizing pulse remover, and said vertical synchronizing signal separator being receptive of the composite synchronizing signal; and a field detector including at least one delay flip-flop means and having a data input terminal connected to an output terminal of said equalizing pulse remover, a trigger input terminal connected to an output terminal of said vertical synchronizing signal separator, and a time constant control terminal connected to an output terminal of said F/V converter; said field discriminating circuit being arranged such that at a time or during a time period upon elapse of a time period from a prescribed leading edge of a rectangular-wave output signal from said vertical synchronizing signal separator, said field detector determines the binary level of an output signal applied by said equalizing pulse remover to said data input terminal for deriving the field discriminating signal of either a high level or a low level.

Claim 9

A synchronizing signal generating circuit according to claim 5, wherein said field detector substantially comprises monostable multivibrator means and D-type flip-flop means, said monostable multivibrator means having a trigger input terminal supplied with an output signal from said vertical synchronizing signal separator, a time constant control terminal supplied with an output signal from said F/V converter, and an output terminal connected to a clock input terminal of said D-type flip-flop means, said D-type flip-flop means having a data input terminal supplied with an output signal from said equalizing pulse remover for deriving an output signal from said D-type flip-flop means as the field discriminating signal.

Claim 10

A synchronizing signal generating circuit according to 5, wherein said field detector comprises first monostable multivibrator means, second monostable multivibrator means, D-type flip-flop means, and negative logic AND gate means, said first monostable multivibrator means having a trigger input terminal supplied with an output signal from said vertical synchronizing signal separator, a time constant control terminal supplied with an output signal from said F/V converter, and an output terminal for applying an output signal to a trigger input terminal of said second monostable multivibrator means, said second monostable multivibrator means having an output terminal for applying a positive output signal to a clock input terminal of said D-type flip-flop means and another output terminal for applying a negative output signal to one input terminal of said negative logic AND gate means, said negative logic AND gate means having another input terminal supplied with an output signal from said equalizing pulse remover, and an output terminal for applying an output signal to a set input terminal of said D-type flip-flop means, said D-type flip-flop means having a data input terminal supplied with a negative output signal from said D-type flip-flop means as the field discriminating signal.

Claim 11

A synchronizing signal generating circuit according to 5, wherein said field detector comprises first monostable multivibrator means, second monostable multivibrator means, D-type flip-flop means, and negative logic AND gate means, said first monostable multivibrator means having a trigger input terminal supplied with an output signal from said vertical synchronizing signal separator, a time constant control terminal supplied with an output signal from said F/V converter, and an output terminal for applying an output signal to a trigger input terminal of said second monostable multivibrator means, said second monostable multivibrator means having an output terminal for applying a positive output signal to a clock input terminal of said D-type flip-flop means and another output terminal for applying a negative output signal to one input terminal of said negative logic AND gate means, said negative logic AND gate means having another input terminal supplied with an output signal from said equalizing pulse remover, and an output terminal for applying an output signal to a set input terminal of said D-type flip-flop means, said D-type flip-flop means having a data input terminal supplied with a negative output signal from said D-type flip-flop means as the field discriminating signal.

Claim 12

A synchronizing signal generating circuit comprising: a field discriminating circuit for deriving a field discriminating signal from a composite synchronizing signal relative to a plurality of composite video signals having different numbers of scanning lines and produced from different video output devices; a frequency synthesizer for multiplying a horizontal synchronizing signal based on said composite synchronizing signal; an F/V converter; an equalizing pulse remover and a vertical synchronizing signal separator which are controlled by said F/V converter, said F/V converter, said equalizing pulse remover, and said vertical synchronizing signal separator being receptive of the composite synchronizing signal; and a field detector including at least one delay flip-flop means and having a data input terminal connected to an output terminal of said equalizing pulse remover, a trigger input terminal connected to an output terminal of said vertical synchronizing signal separator, and a time constant control terminal connected to an output terminal of said F/V converter; said field discriminating circuit being arranged such that at a time or during a time period upon elapse of a time period from a prescribed leading edge of a rectangular-wave output signal from said vertical synchronizing signal separator, said field detector determines the binary level of an output signal applied by said equalizing pulse remover to said data input terminal for deriving the field discriminating signal of either a high level or a low level, the arrangement being such that an output signal from said equalizing pulse remover is applied to a reference input terminal of said frequency synthesizer to enable the frequency synthesizer to produce from an output terminal thereof a signal that is obtained by multiplying the horizontal synchronizing signal.

Claim 13

A synchronizing signal generating circuit comprising: a field discriminating circuit for deriving a field discriminating signal from a composite synchronizing signal relative to a plurality of composite video signals having different numbers of scanning lines and produced from different video output devices; a frequency synthesizer for multiplying a horizontal synchronizing signal based on said composite synchronizing signal; an F/V converter; an equalizing pulse remover and a vertical synchronizing signal separator which are controlled by said F/V converter, said F/V converter, said equalizing pulse remover, and said vertical synchronizing signal separator being receptive of the composite synchronizing signal; and a field detector including at least one delay flip-flop means and having a data input terminal connected to an output terminal of said equalizing pulse remover, a trigger input terminal connected to an output terminal of said vertical synchronizing signal separator, and a time constant control terminal connected to an output terminal of said F/V converter; said field discriminating circuit being arranged such that at a time or during a time period upon elapse of a time period from a prescribed leading edge of a rectangular-wave output signal from said vertical synchronizing signal separator, said field detector determines the binary level of an output signal applied by said equalizing pulse remover to said data input terminal for deriving the field discriminating signal of either a high level or a low level, the arrangement being such that an output signal from said equalizing pulse remover is applied to a reference input terminal of said frequency synthesizer to enable the frequency synthesizer to produce from an output terminal thereof a signal that is obtained by multiplying the horizontal synchronizing signal.

Claim 14

A synchronizing signal generating circuit comprising: a field discriminating circuit for deriving a field discriminating signal from a composite synchronizing signal relative to a plurality of composite video signals having different numbers of scanning lines and produced from different video output devices; a frequency synthesizer including at least a prescaler for multiplying a horizontal synchronizing signal based on said composite synchronizing signal; an F/V converter; an equalizing pulse remover and a vertical synchronizing signal separator which are controlled by said F/V converter, said F/V converter, said equalizing pulse remover, and said vertical synchronizing signal separator being receptive of the composite synchronizing signal; and a field detector including at least one delay flip-flop means and having a data input terminal connected to an output terminal of said equalizing pulse remover, a trigger input terminal connected to an output terminal of said vertical synchronizing signal separator, and a time constant control terminal connected to an output terminal of said F/V converter; said field discriminating circuit being arranged such that at a time or during a time period upon elapse of a time period from a prescribed leading edge of a rectangular-wave output signal from said vertical synchronizing signal separator, said field detector determines the binary level of an output signal applied by said equalizing pulse remover to said data input terminal for deriving the field discriminating signal of either a high level or a low level, the arrangement being such that an output signal from said equalizing pulse remover is applied to a reference input terminal of said frequency synthesizer and an output signal from said F/V converter is applied as a control signal as said prescaler to enable the prescaler to produce from an output terminal of said frequency synthesizer a signal that is obtained by multiplying the horizontal synchronizing signal.

Claim 15

A synchronizing signal generating circuit comprising: a field discriminating circuit for deriving a field discriminating signal from a composite synchronizing signal relative to a plurality of composite video signals having different numbers of scanning lines and produced from different video output devices; a frequency synthesizer including at least a prescaler for multiplying a horizontal synchronizing signal based on said composite synchronizing signal; an F/V converter; an equalizing pulse remover and a vertical synchronizing signal separator which are controlled by said F/V converter, said F/V converter, said equalizing pulse remover, and said vertical synchronizing signal separator being receptive of the composite synchronizing signal; and a field detector including at least one delay flip-flop means and having a data input terminal connected to an output terminal of said equalizing pulse remover, a trigger input terminal connected to an output terminal of said vertical synchronizing signal separator, and a time constant control terminal connected to an output terminal of said F/V converter; said field discriminating circuit being arranged such that at a time or during a time period upon elapse of a time period from a prescribed leading edge of a rectangular-wave output signal from said vertical synchronizing signal separator, said field detector determines the binary level of an output signal applied by said equalizing pulse remover to said data input terminal for deriving the field discriminating signal of either a high level or a low level, the arrangement being such that an output signal from said equalizing pulse remover is applied to a reference input terminal of said frequency synthesizer and an output signal from said F/V converter is applied as a control signal as said prescaler to enable the prescaler to produce from an output terminal of said frequency synthesizer a signal that is obtained by multiplying the horizontal synchronizing signal.