US4827157A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Periodic signal generator circuit
Assignee: Mitsubishi Electric Corp
•
Filing: 1987-11-27
•
Granted: 1989-05-02
•
Expires: 2007-11-27
Abstract
Abstract In a periodic signal generator circuit, logical threshold values of an inverter for inverting an output signal of a first logical gate circuit (1) and inputting the same to a second logical gate circuit (2) and an inverter (40) for inverting an output signal of the second logical gate circuit (2) and inputting the same to the first logical gate circuit are set low, so that the time when an output signal of one of the logical gate circuits (1, 2) is inverted by inverting an output signal of the other logical gate circuit is delayed. Thus, the periodic signal generator circuit generates a so-called two-phase non-overlapped clock signal.
Inventors
- 👤 Hirohisa Machida
- 👤 Takeo Nakabayashi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 18:03
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/15; H03K5/151; H03K5/1515
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
169 words
In a periodic signal generator circuit comprising at least a first logical gate circuit, a second logical gate circuit, a first inverter circuit, a second inverter circuit and a third inverter circuit, said first logical gate circuit receiving an output signal of said second logical gate circuit inputted through said second inverter circuit and a periodic signal, and said second logical gate circuit receiving an output signal of said first logical gate circuit through said first inverter circuit and said periodic signal through said third inverter circuit, the output signal of one of the logical gate circuits being inverted by inverting the output signal of the other logical gate circuit so that complementary periodic signals are outputted respectively from said first logical gate circuit and said second logical gate circuit, an improvement for increasing separation between said complementary periodic signals, where said first inverter circuit and said second inverter circuit are constructed to have thresholds with the range of 0.2 to 0.4 Vcc wherein Vcc is a supply voltage.
Claim 2
Dependent Claim
169 words
In a periodic signal generator circuit comprising at least a first logical gate circuit, a second logical gate circuit, a first inverter circuit, a second inverter circuit and a third inverter circuit, said first logical gate circuit receiving an output signal of said second logical gate circuit inputted through said second inverter circuit and a periodic signal, and said second logical gate circuit receiving an output signal of said first logical gate circuit through said first inverter circuit and said periodic signal through said third inverter circuit, the output signal of one of the logical gate circuits being inverted by inverting the output signal of the other logical gate circuit so that complementary periodic signals are outputted respectively from said first logical gate circuit and said second logical gate circuit, an improvement for increasing separation between said complementary periodic signals, where said first inverter circuit and said second inverter circuit are constructed to have thresholds with the range of 0.2 to 0.4 Vcc wherein Vcc is a supply voltage.
Claim 3
Dependent Claim
32 words
A periodic signal generator in accordance with claim 1, wherein the logical threshold values of said first inverter circuit and said second inverter circuit are constructed to have thresholds of approximately 0.3Vcc.
Claim 4
Dependent Claim
108 words
A periodic signal generator circuit in accordance with claim 1, wherein said first inverter circuit and said second inverter circuit together comprise a p type transistor and an n type transistor, each of said transistors having a channel formed by a source region, a drain region and a channel region between said source region and said drain region, a lead pattern interconnecting said p type transistor and said n type transistor, said p type transistor having a channel providing a threshold with the range of 0.2 to 0.4 Vcc, and said n type transistor having a channel providing a threshold with the range of 0.2 to 0.4 Vcc.
Claim 5
Dependent Claim
114 words
A periodic signal generator circuit having increased separation between complementary periodic signal outputs, comprising: first and second logical gate circuits; first, second inverter circuits each having an input threshold between 0.2 and 0.4 Vcc where Vcc is a supply voltage; and a third inverter; wherein said first logical gate circuit receives an output signal of said second logical gate circuit inputted through said second inverter circuit and a periodic signal, and said second logical gate circuit receives an output signal of said first logical gate circuit through said first inverter circuit and said periodic signal through said third inverter circuit, said complementary periodic signals outputted respectively from said first and second logical gate circuits.
Claim 6
Dependent Claim
114 words
A periodic signal generator circuit having increased separation between complementary periodic signal outputs, comprising: first and second logical gate circuits; first, second inverter circuits each having an input threshold between 0.2 and 0.4 Vcc where Vcc is a supply voltage; and a third inverter; wherein said first logical gate circuit receives an output signal of said second logical gate circuit inputted through said second inverter circuit and a periodic signal, and said second logical gate circuit receives an output signal of said first logical gate circuit through said first inverter circuit and said periodic signal through said third inverter circuit, said complementary periodic signals outputted respectively from said first and second logical gate circuits.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-05-01 | 1992-10-31 | 1993-05-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-05-01 | 1996-10-31 | 1997-05-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-05-01 | 2000-10-31 | 2001-05-02 | $7700.00 | Window Closed / Lapsed |