Subscriber telephone equipment test apparatus

Claim 2

An impedance termination network connected between a device under test and a frequency selective voltmeter, said network comprising, first resistive means, second resistive means, third resistive means, a first switch means having first, second and third positions corresponding to three successive frequency ranges, means coupling the first, second and third resistive means to the respective first, second and third positions whereby the position selection corresponds to resistive means selection, and a second switch means having two positions with each position for selection of either differential or common mode signals.

Claim 3

An impedance termination network as set forth in claim 1 wherein each resistive means comprises a pair of series connected resistors.

Claim 4

An impedance termination network has set forth in claim 2 wherein said first switch means has at least two separate poles having defined thereat said first, second and third positions and further including a first capacitor coupled to a first pole of said first switch means and a second capacitor coupled to a second pole of said first switch means.

Claim 5

An impedance termination network as set forth in claim 3 including a third pole of said first switch means and a filter means connected to the third pole of said first switch means.

Claim 6

A surge simulation circuit including a high voltage supply, a capacitor network, switch means for enabling charging and discharging of said capacitor network, said capacitor network being charged from said high voltage supply and discharged into a load, said capacitor network comprising, a first capacitance network, a second capacitance network, a third capacitance network, a switch network for interconnecting said capacitance networks in parallel between terminals of the capacitor network, said switch network including a plurality of switches that may be selectively opened or closed depending upon the desired capacitance of the overall network.

Claim 7

A surge simulation circuit including a high voltage supply, a capacitor network, switch means for enabling charging and discharging of said capacitor network, said capacitor network being charged from said high voltage supply and discharged into a load, said capacitor network comprising, a first capacitance network, a second capacitance network, a third capacitance network, a switch network for interconnecting said capacitance networks in parallel between terminals of the capacitor network, said switch network including a plurality of switches that may be selectively opened or closed depending upon the desired capacitance of the overall network.

Claim 8

A surge simulation circuit as set forth in claim 5 further including a resistance element an inductance element in series with said capacitor network and coupling to a device under test.

Claim 9

A surge simulation circuit as set forth in claim 6 wherein each said capacitance network comprises a plurality of series connected capacitors.

Claim 10

A surge simulation circuit as set forth in claim 7 wherein said plurality of switches comprise four switches forming with said capacitance networks, a ladder network.

Claim 11

A surge simulation circuit as set forth in claim 8 further including a resistor in parallel with each of said capacitors.

Claim 12

A network for measuring signal balance across a telephone signal transmission pair, comprising, a first amplifier means coupled to one input line, a second amplifier means coupled to the other input line, a summing amplifier having two inputs coupled from the respective first and second amplifier means, first and second input networks each comprising an input capacitor connected in series with a phase shift compensation network.

Claim 13

A network for measuring signal balance across a telephone signal transmission pair, comprising, a first amplifier means coupled to one input line, a second amplifier means coupled to the other input line, a summing amplifier having two inputs coupled from the respective first and second amplifier means, first and second input networks each comprising an input capacitor connected in series with a phase shift compensation network.

Claim 14

A network as set forth in claim 10 further including a trimmer capacitor connected in parallel with one of said input capacitors so as to match capacitance values to within on the order of 0.1%.

Claim 15

A network as set forth in claim 11 wherein said phase shift compensation network comprises an R-C circuit.

Claim 16

A network as set forth in claim 12 wherein one of the capacitors of said R-C circuit is a variable capacitor.

Claim 17

A network as set forth in claim 13 further including a potentiometer coupling from the output of said second amplifier means to one of the inputs of the said summing amplifier.