Linear feedback shift register circuit, of systolic architecture

Claim 1

A linear feedback shift register circuit suitable for providing respective digital samples (Sj) at successive time instants, each of which samples represents a linear combination of prior digital samples (Sj-1 to Sj-N) and comprises M significant bits together with an optional addition of X sign extension bits, where X may optionally be zero, said circuit comprising N similar cells (C1 to CN) each of which forms a bit flow path comprising in series between a main input and a main output (EP1 to EPN, and SP1 to SPN) of said cell: a P-bit upstream register (RGE1 to RGEN); a weighting operator (OP1 to OPN); a two-input combining operator (OC1 to OCN); and a Q-bit downstream register (RGS1 to RGSN); with the output from the upstream register (RGE1 to RGEN) and one of the two inputs to the combining operator (OC1 to OCN) respectively constituting a secondary output and a secondary input (SS1 to SSN, and ES1 to ESN) of the cell suitable for being respectively connected to a main input and to a main output of a following cell in the circuit, and with the main output (SP1) of the first cell being fed back to the main input (EP1) of said cell in order to allow the digital samples produced to be recirculated, the LFSR circuit being characterized in that said upstream registers (RGE1 to RGEN), and said downstream registers (RGS1 to RGSN) of each cell are serial shift registers, and in that the sum P+Q of their lengths is equal to the total length M+X of each of the digital samples.