Hybrid encoder

Claim 2

A hybrid encoder for encoding video signals which represent picture elements of a video picture and which are arranged in equally large data blocks, each data block being compared with the corresponding data block of the previous video picture by means of a subtractor and the corresponding data block of the previous video picture being derived from a picture store; a difference block being obtained by the subtractor and supplied to a first processing circuit (F) which subjects said difference block to a matrix transformation, such transformation being inversed in a feedback path by a second processing circuit (IF) with the inverse matrix to regain said difference block; the regained difference block being applied to a first input of an adder and data blocks from the picture store being applied to a second input of the adder, the output of the adder being connected to the data input of the picture store; characterized in that the first processing circuit (F) is succeeded by a third processing circuit (T) which performs a matrix transformation having a low-pass character on the transformed blocks from the first processing circuit (F) and in that a fourth processing circuit (FTI) is arranged between the output (A) of the picture store (BS) and the second input of the adder (AR); said fourth processing circuit performing a matrix transformation which has the same effect as the successively performed matrix operations of the first (F), third (T) and second (IF) processing circuits.

Claim 3

A hybrid encoder as claimed in claim 1, wherein the matrices of the third (T) and fourth (FTI) processing circuits are adaptively varied in dependence on the video signals to be encoded.

Claim 4

A hybrid encoder as claimed in claim 1, wherein the third processing circuit (T) which performs the matrix operations having a low-pass character, the matrix is a diagonal matrix, and a cosine transformation is performed in the matrix transformation of the first processing circuit (F).

Claim 5

A hybrid encoder as claimed in claim 3, wherein the matrices of the third (T) and fourth (FTI) processing circuits are adaptively varied in dependence on the video signals to be encoded.

Claim 6

A hybrid encoder for encoding video signals which represent picture elements of a video picture and which are arranged in equally large data blocks, each data block being compared with the corresponding data block of the previous video picture by means of a subtractor and the corresponding data block of the previous video picture being derived from a picture store; a difference block being obtained by the subtractor and supplied to a first processing circuit (F) which subjects said difference block to a matrix transformation, such transformation being inversed in a feedback path by a second processing circuit (IF) with the inverse matrix to regain said difference block; the regained difference block being supplied to a first input of an adder and data blocks from the picture store being supplied to a second input of the adder, the output of the adder being connected to the data input of the picture store; characterized in that a third processing circuit (FTI) is arranged between the subtractor (SR) and the first processing circuit (F), said third processing circuit performing a matrix transformation having a low-pass character on each data block prior to transformation thereof in processing circuit (F); and a fourth processing circuit (FTI) is arranged between the output (A) of the picture store (BS) and the second input of the adder (AR), said fourth processing circuit also performing a matrix transformation having a low pass character and which is identical to the transformation performed by said third processing circuit.

Claim 7

A hybrid encoder for encoding video signals which represent picture elements of a video picture and which are arranged in equally large data blocks, each data block being compared with the corresponding data block of the previous video picture by means of a subtractor and the corresponding data block of the previous video picture being derived from a picture store; a difference block being obtained by the subtractor and supplied to a first processing circuit (F) which subjects said difference block to a matrix transformation, such transformation being inversed in a feedback path by a second processing circuit (IF) with the inverse matrix to regain said difference block; the regained difference block being supplied to a first input of an adder and data blocks from the picture store being supplied to a second input of the adder, the output of the adder being connected to the data input of the picture store; characterized in that a third processing circuit (FTI) is arranged between the subtractor (SR) and the first processing circuit (F), said third processing circuit performing a matrix transformation having a low-pass character on each data block prior to transformation thereof in processing circuit (F); and a fourth processing circuit (FTI) is arranged between the output (A) of the picture store (BS) and the second input of the adder (AR), said fourth processing circuit also performing a matrix transformation having a low pass character and which is identical to the transformation performed by said third processing circuit.

Claim 8

A hybrid encoder as claimed in claim 5 further comprising a buffer store (P) for said regained difference block, and wherein the low-pass matrix transformation performed by the third and fourth processing circuits have cut-off frequencies which are changed in dependence upon the filling level of such buffer store.

Claim 9

A hybrid encoder for encoding video signals which represent picture elements of a video picture and which are arranged in equally large data blocks, each data block being compared with the corresponding data block of the previous video picture by means of a subtractor and the corresponding data block of the previous video picture being derived from a picture store; a difference block being obtained by the subtractor and supplied to a first processing circuit (F) which subjects said difference block to a matrix transformation, such transformation being inversed in a feedback path by a second processing circuit (IF) with the inverse matrix to regain said difference block; the regained difference block being supplied to a first input of an adder and data blocks from the picture store being supplied to a second input of the adder, the output of the adder being connected to the data input of the picture store; characterized in that a third processing circuit (T1) is arranged between the subtractor (SR) and the first processing circuit (F) which performs a matrix transformation having a low-pass character on each data block before comparison in the subtractor (SR); and a fourth processing circuit (T2) also performing a matrix transformation having a low-pas character is arranged immediately behind the output (A) of the picture store (BS).

Claim 10

A hybrid encoder for encoding video signals which represent picture elements of a video picture and which are arranged in equally large data blocks, each data block being compared with the corresponding data block of the previous video picture by means of a subtractor and the corresponding data block of the previous video picture being derived from a picture store; a difference block being obtained by the subtractor and supplied to a first processing circuit (F) which subjects said difference block to a matrix transformation, such transformation being inversed in a feedback path by a second processing circuit (IF) with the inverse matrix to regain said difference block; the regained difference block being supplied to a first input of an adder and data blocks from the picture store being supplied to a second input of the adder, the output of the adder being connected to the data input of the picture store; characterized in that a third processing circuit (T1) is arranged between the subtractor (SR) and the first processing circuit (F) which performs a matrix transformation having a low-pass character on each data block before comparison in the subtractor (SR); and a fourth processing circuit (T2) also performing a matrix transformation having a low-pas character is arranged immediately behind the output (A) of the picture store (BS).

Claim 11

A hybrid encoder as claimed in claim 7, wherein the low-pass effect of the third processing circuit (T1) which is arranged between said subtractor (SR) and the first processing circuit (F) is smaller than the low-pass effect of the fourth processing circuit (T2) which filters the data blocks from the picture store.

Claim 12

A hybrid encoder as claimed in claim 7, further comprising a buffer store (P) for said regained difference block and wherein the low-pass matrix transformation performed by the third and fourth processing circuits have cut-off frequencies which are changed in dependence upon the filling level of such buffer store.

Claim 13

A hybrid decoder for decoding video signals which are encoded by a hybrid encoder as claimed in any of claims 1, 5, or 7, and which present picture elements of a video picture arranged in equally large data blocks; such decoder comprising an input buffer memory for receiving such data blocks and a processing circuit for subjecting such data block to a matrix transformation identical to that performed by the second processing circuit (IF) of the hybrid encoder, an output of the processing circuit of said decoder being connected to a first input of an adder, a second input of the adder being connected to an output of a picture store (BS) which is functionally the same as the picture store of the hybrid encoder, the output of the adder being connected to the input of said picture store (BS); characterized in that a further processing circuit is arranged between the output of the picture store (BS) and said second input of the adder, such further processing circuit performing a matrix transformation having a low-pass character on the data blocks at the output of the picture store (BS) identical to the matrix transformation having a low-pass character performed by the fourth processing circuit (FT1 or T2) of the hybrid encoder.