Differential amplifier circuit

Claim 2

A differential amplifier circuit comprising (a) a pair of mutually complementary bit lines connected to a row of memory cells arranged in rows and columns, (b) first and second load transistors each of the load transistors being implemented by a p-channel MOS field-effect transistor, (c) first and second amplifier transistors each of the amplifier transistors being implemented by an n-channel MOS field-effect transistor, (d) said load transistors having their respective gates commonly connected to the respective drains of the first load transistor and the first amplifier transistor, said first and second amplifier transistors having their respective gates connected to said complementary bit lines, respectively, (e) an activating transistor through which said first and second amplifier transistors have their respective sources commonly connected to a first supply voltage line, said activating transistor being implemented by an n-channel MOS field-effect transistor and having its drain connected to the respective sources of said first and second amplifier transistors through a common node, its source connected to said first supply voltage line, and its gate connected to a clock supply line through which an active-high clock signal is to be supplied, (f) said second load transistor and said second amplifier transistor having their respective drains commonly connected through a node to an output line, and (g) first and second current cutoff transistors each of which is implemented by a p-channel MOS field-effect transistor, the first and second current cutoff transistors having their respective sources connected to a second voltage supply, their respective drains connected to the sources of the first and second load transistors, respectively, and their respective gates connect to said complementary bit lines through first and second inverters, respectively.

Claim 3

A differential amplifier circuit comprising (a) a pair of mutually complementary bit lines connected to a row of memory cells arranged in rows and columns, (b) first and second load transistors each of the load transistors being implemented by a p-channel MOS field-effect transistor, (c) first and second amplifier transistors each of the amplifier transistors being implemented by an n-channel MOS field-effect transistor, (d) said load transistors having their respective gates commonly connected to the respective drains of the first load transistor and the first amplifier transistor, said first and second amplifier transistors having their respective gates connected to said complementary bit lines, respectively, (e) first and second activating transistors through which said first and second amplifier transistors have their respective sources commonly connected to a first supply voltage line, said first and second activating transistors being implemented by an n-channel MOS field-effect transistors and having their respective drains connected to the respective sources of the first and second amplifier transistors their respective sources connected to said first supply line, and their respective gates commonly connected to a clock supply line through which an active-high clock signal is to be supplied, (f) said second load transistor and said second amplifier transistor having their respective drains commonly connected through a node to an output line, and (g) first and second current cutoff transistors each of which is implemented by a p-channel MOS field-effect transistor, the first and second current cutoff transistors having their respective sources connected to a second voltage supply, their respective drains connected to the sources of the first and second load transistors, respectively, and their respective gates connected to said complementary bit lines through first and second inverters, respectively.

Claim 4

A differential amplifier circuit comprising (a) a pair of mutually complementary bit lines connected to a row of memory cells arranged in rows and columns, (b) first and second load transistors each of the load transistors being implemented by a p-channel MOS field-effect transistor, (c) first and second amplifier transistors each of the amplifier transistors being implemented by an n-channel MOS field-effect transistor, (d) said load transistors having their respective gates commonly connected to the respective drains of the first load transistor and the first amplifier transistor, said first and second amplifier transistors having their respective gates connected to said complementary bit lines, respectively, (e) first and second activating transistors through which said first and second amplifier transistors have their respective sources commonly connected to a first supply voltage line, said first and second activating transistors being implemented by an n-channel MOS field-effect transistors and having their respective drains connected to the respective sources of the first and second amplifier transistors their respective sources connected to said first supply line, and their respective gates commonly connected to a clock supply line through which an active-high clock signal is to be supplied, (f) said second load transistor and said second amplifier transistor having their respective drains commonly connected through a node to an output line, and (g) first and second current cutoff transistors each of which is implemented by a p-channel MOS field-effect transistor, the first and second current cutoff transistors having their respective sources connected to a second voltage supply, their respective drains connected to the sources of the first and second load transistors, respectively, and their respective gates connected to said complementary bit lines through first and second inverters, respectively.

Claim 5

A differential amplifier circuit comprising (a) a pair of mutually complementary input lines, (b) first and second amplifier transistors each of the amplifier transistors being implemented by an n-channel MOS field-effect transistor, said first and second amplifier transistors having their respective gates connected to said complementary input lines, respectively, (c) an activating transistor through which said first and second amplifier transistors have their respective sources commonly connected to a first supply voltage line, said activating transistor being implemented by an n-channel MOS field-effect transistor and having its drain connected to the respective sources of said first and second amplifier transistors through a common node, its source connected to said first supply voltage line, and its gate connected to a clock supply line through which an active-high clock signal is to be supplied, (d) first and second current cutoff transistors each of which is implemented by a p-channel MOS field-effect transistor, the first and second current cutoff transistors having their respective sources connected to a second voltage supply line, and their respective drains connected to the drains of the first and second amplifier transistors, respectively, (e) said first current cutoff transistor and said first amplifier transistor having their respective drains commonly connected through a first sense node to a first output line, and said second current cutoff transistor and said second amplifier transistor having their respective drains commonly connected through a second sense node to a second output line, and (f) first and second inverters through which said first and second current cutoff transistors have their respective gates connected to said complementary input lines, respectively, each of said first and second inverters comprising a series combination of a p-channel field-effect transistor having its source connected to said second voltage supply line and an n-channel field-effect transistor having its drain connected to the drain of the p-channel transistor of the same inverter and having its source connected to said first voltage supply line, the p-channel and n-channel transistors of the first inverter having their respective gates commonly connected to one of said input lines the p-channel and n-channel transistors of the second inverter having their respective gates commonly connected to the other of said input lines, the common drains of the transistors of said first inverter being connected to the gate of said second current cutoff transistor and the common drains of the transistors of said second inverter being connected at a second common node to the gate of said first current cutoff transistor.

Claim 6

A differential amplifier circuit comprising (a) a pair of mutually complementary input lines, (b) first and second amplifier transistors each of the amplifier transistors being implemented by an n-channel MOS field-effect transistor, said first and second amplifier transistors having their respective gates connected to said complementary input lines, respectively, (c) an activating transistor through which said first and second amplifier transistors have their respective sources commonly connected to a first supply voltage line, said activating transistor being implemented by an n-channel MOS field-effect transistor and having its drain connected to the respective sources of said first and second amplifier transistors through a common node, its source connected to said first supply voltage line, and its gate connected to a clock supply line through which an active-high clock signal is to be supplied, (d) first and second current cutoff transistors each of which is implemented by a p-channel MOS field-effect transistor, the first and second current cutoff transistors having their respective sources connected to a second voltage supply line, and their respective drains connected to the drains of the first and second amplifier transistors, respectively, (e) said first current cutoff transistor and said first amplifier transistor having their respective drains commonly connected through a first sense node to a first output line, and said second current cutoff transistor and said second amplifier transistor having their respective drains commonly connected through a second sense node to a second output line, and (f) first and second inverters through which said first and second current cutoff transistors have their respective gates connected to said complementary input lines, respectively, each of said first and second inverters comprising a series combination of a p-channel field-effect transistor having its source connected to said second voltage supply line and an n-channel field-effect transistor having its drain connected to the drain of the p-channel transistor of the same inverter and having its source connected to said first voltage supply line, the p-channel and n-channel transistors of the first inverter having their respective gates commonly connected to one of said input lines the p-channel and n-channel transistors of the second inverter having their respective gates commonly connected to the other of said input lines, the common drains of the transistors of said first inverter being connected to the gate of said second current cutoff transistor and the common drains of the transistors of said second inverter being connected at a second common node to the gate of said first current cutoff transistor.

Claim 7

A differential amplifier circuit comprising (a) a pair of mutually complementary input lines, (b) first and second amplifier transistors each of the amplifier transistors being implemented by an n-channel MOS field-effect transistor, said first and second amplifier transistors having their respective gates connected to said complementary input lines, respectively, (c) an activating transistor through which said first and second amplifier transistors have their respective sources commonly connected to a first supply voltage line, said activating transistor being implemented by an n-channel MOS field-effect transistor and having its drain connected to the respective sources of said first and second amplifier transistors through a common node, its source connected to said first supply voltage line, and its gate connected to a clock supply line through which an active-high clock signal is to be supplied, (d) first and second current cut off transistors each of which is implemented by a p-channel MOS field-effect transistor, the first and second current cutoff transistors having their respective sources connected to a second voltage supply, and their respective drains connected to the drains of the first and second amplifier transistors, respectively, (e) said first current cutoff transistor and said first amplifier transistor having their respective drains commonly connected through a first sense node to a first output line, and said second current cutoff transistor and said second amplifier transistor having their respective drains commonly connected through a second sense node to a second output line, (f) first and second inverters through which said first and second current cutoff transistors have their respective gates connected to said complementary input lines, respectively, each of said first and second inverters comprising a series combination of a p-channel field-effect transistor having its source connected to said second voltage supply line and an n-channel field-effect transistor having its drain connected to the drain of the p-channel transistor of the same inverter and having its source connected to said first voltage supply line, the p-channel and n-channel transistors of the first inverter having their respective gates commonly connected to one of said input lines and the p-channel and n-channel transistors of the second inverter having their respective gates commonly connected to the other of said input lines, the common drains of the transistors of said first inverter being connected to the gate of said second current cutoff transistor and the common drains of the transistors of said second inverter being connected to the gate of said first field-effect transistor, (g) first and second precharge transistors each implemented by a p-channel MOS field-effect transistor, the first and second precharge transistors being provided in parallel with said first and second current cutoff transistors, respectively, and having their respective sources connected to said second voltage supply line and their respective drains connected to the drains of said first and second amplifier transistors through said first and second sense nodes, respectively, and (h) a voltage equalizer transistor implemented by a p-channel MOS field-effect transistor, the voltage equalizer transistor having one of its source and drain connected to the drains of the first current cutoff and precharge transistors and the other of its source and drain connected to the drains of the second current cutoff and precharge transistors, said first and second precharge transistors and said voltage equalizer transistor having their respective gates connected commonly to said clock supply line.

Claim 8

A differential amplifier circuit comprising (a) a pair of mutually complementary input lines, (b) first and second amplifier transistors each of the amplifier transistors being implemented by an n-channel MOS field-effect transistor, said first and second amplifier transistors having their respective gates connected to said complementary input lines, respectively, (c) an activating transistor through which said first and second amplifier transistors have their respective sources commonly connected to a first supply voltage line, said activating transistor being implemented by an n-channel MOS field-effect transistor and having its drain connected to the respective sources of said first and second amplifier transistors through a common node, its source connected to said first supply voltage line, and its gate connected to a clock supply line through which an active-high clock signal is to be supplied, (d) first and second current cut off transistors each of which is implemented by a p-channel MOS field-effect transistor, the first and second current cutoff transistors having their respective sources connected to a second voltage supply, and their respective drains connected to the drains of the first and second amplifier transistors, respectively, (e) said first current cutoff transistor and said first amplifier transistor having their respective drains commonly connected through a first sense node to a first output line, and said second current cutoff transistor and said second amplifier transistor having their respective drains commonly connected through a second sense node to a second output line, (f) first and second inverters through which said first and second current cutoff transistors have their respective gates connected to said complementary input lines, respectively, each of said first and second inverters comprising a series combination of a p-channel field-effect transistor having its source connected to said second voltage supply line and an n-channel field-effect transistor having its drain connected to the drain of the p-channel transistor of the same inverter and having its source connected to said first voltage supply line, the p-channel and n-channel transistors of the first inverter having their respective gates commonly connected to one of said input lines and the p-channel and n-channel transistors of the second inverter having their respective gates commonly connected to the other of said input lines, the common drains of the transistors of said first inverter being connected to the gate of said second current cutoff transistor and the common drains of the transistors of said second inverter being connected to the gate of said first field-effect transistor, (g) first and second precharge transistors each implemented by a p-channel MOS field-effect transistor, the first and second precharge transistors being provided in parallel with said first and second current cutoff transistors, respectively, and having their respective sources connected to said second voltage supply line and their respective drains connected to the drains of said first and second amplifier transistors through said first and second sense nodes, respectively, and (h) a voltage equalizer transistor implemented by a p-channel MOS field-effect transistor, the voltage equalizer transistor having one of its source and drain connected to the drains of the first current cutoff and precharge transistors and the other of its source and drain connected to the drains of the second current cutoff and precharge transistors, said first and second precharge transistors and said voltage equalizer transistor having their respective gates connected commonly to said clock supply line.