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US4824192A
Expired / Lapsed
US
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Optical processing
Assignee: BAE Systems PLC
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Filing: 1987-10-16
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Granted: 1989-04-25
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Expires: 2007-10-16
Abstract
Abstract An optical processor includes a non-linear spatial light modulator defining an array of logic gates and having an output plane 10 ) and an input plane 12. The array is made up of a plurality of cells 14 each containing a plurality of logic gates 16. A lenslet array 18 comprising an array of lenslets 20 associated one with each cell 14 respectively focusses the oututs of the cells onto respective facets 22 of a holographic array 24. Each facet of the holographic array defines a predetermined mapping or routing configuration to map the respective cell onto the input plane 12. The cells may be mapped either precisely onto the predetermined cell of the input plane or in cell-shifted fashion. An optical processor is described which employs the arrangement illustrated in FIG. 1 to enable asembly of a plurality of similar interacting modules for implementing a regular algorithm such as a fast multiplier array.
Inventors
- 👤 Nicholas C. Roberts
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 18:05
CPC Classifications
G; G06; G06E; G06E1/00; G06E1/02; G06E1/04
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
325 words
An optical processor including a series of M similar logic modules, each logic module comprising N logic gates and a set of connections between a plurality of logic gates within each logic module, the set of connections being the same for each logic module, said logic modules being connected with each other to form an optical processor, said logic modules and said connections comprising: a logic gate array having an input plane and an output plane, including (N×M) logic gates, each logic gate having an input and an output on the input plane and the output plane, respectively, and said logic gates arranged in the form of N cells, each cell including M logic gates, the number of cells (N) defining the number of gates in each module of the optical processor and the number of gates (M) in each cell defining the number of modules in the processor; and a holographic array having M facets, each facet having incident thereon output signals from a respective associated cell of said logic gate array, each of said facets comprising means for providing a predetermined mapping function and for causing output signals from said associated cell to be mapped onto said input plane of the array, at least one of said facets comprising a means for providing a cell-to-cell mapping function and for causing all outputs from an associated cell to be mapped onto the corresponding inputs of a respective predetermined cell, and at least one of said facets comprising a means for providing a cell-shifted mapping function which causes only some of said outputs from an associated cell to be mapped onto the inputs of a respective predetermined cell, wherein said at least one facet comprising means for providing a cell-to-cell mapping function determines said set of connections between logic gates within each logic module and said at least one facet comprising means for providing a cell-shifted mapping function determines the connections between said logic modules.
Claim 2
Dependent Claim
325 words
An optical processor including a series of M similar logic modules, each logic module comprising N logic gates and a set of connections between a plurality of logic gates within each logic module, the set of connections being the same for each logic module, said logic modules being connected with each other to form an optical processor, said logic modules and said connections comprising: a logic gate array having an input plane and an output plane, including (N×M) logic gates, each logic gate having an input and an output on the input plane and the output plane, respectively, and said logic gates arranged in the form of N cells, each cell including M logic gates, the number of cells (N) defining the number of gates in each module of the optical processor and the number of gates (M) in each cell defining the number of modules in the processor; and a holographic array having M facets, each facet having incident thereon output signals from a respective associated cell of said logic gate array, each of said facets comprising means for providing a predetermined mapping function and for causing output signals from said associated cell to be mapped onto said input plane of the array, at least one of said facets comprising a means for providing a cell-to-cell mapping function and for causing all outputs from an associated cell to be mapped onto the corresponding inputs of a respective predetermined cell, and at least one of said facets comprising a means for providing a cell-shifted mapping function which causes only some of said outputs from an associated cell to be mapped onto the inputs of a respective predetermined cell, wherein said at least one facet comprising means for providing a cell-to-cell mapping function determines said set of connections between logic gates within each logic module and said at least one facet comprising means for providing a cell-shifted mapping function determines the connections between said logic modules.
Claim 3
Dependent Claim
27 words
An optical processor as claimed in claim 1, which includes focussing means for focussing the output of each cell onto the respective facet of the holographic array.
Claim 4
Dependent Claim
35 words
An optical processor as claimed in claim 2, wherein said focussing means comprises a lenslet array, each lenslet of the array focussing the output of a cell onto the respective facet of the holographic array.
Claim 5
Dependent Claim
18 words
An optical processor as claimed in claim 3, wherein said lenslet array comprises an array of diffractive elements.
Claim 6
Dependent Claim
18 words
An optical processor as claimed in claim 3 wherein said lenslet array comprises an array of refractive elements.
Claim 7
Dependent Claim
19 words
An optical processor as claimed in claim 1, wherein said logic gate array comprises a liquid crystal light valve.
Claim 8
Dependent Claim
24 words
An optical processor according to claim 1, wherein each of said logic modules is a full adder and said modules comprise a multiplier array.
Claim 9
Independent Claim
202 words
A method of processing optical data, comprising the steps of: providing a logic gate array having an input plane and output plane, said logic gate array including a plurality of logic gates, each gate having an input and an output in the input plane and the output plane, respectively; grouping said logic gates on said logic gate array into a series of N cells, each cell containing M logic gates; mapping the outputs of said logic gates of at least one of said cells onto the input plane of the array in cell-to-cell fashion such that all outputs of a cell-to-cell mapped cell are mapped onto the corresponding inputs of a respective predetermined cell; and mapping the outputs of the logic gates of at least one of said cells onto the input plane array in cell-shifted fashion so that only some of the outputs from a cell-shifted mapped cell are mapped onto the corresponding inputs of a respective predetermined cell, whereby a series of M similar interconnected logic modules are defined, each logic module comprising N logic gates and a set of connections between a plurality of logic gates within the module, said set of connections being the same for each module.
Claim 10
Independent Claim
202 words
A method of processing optical data, comprising the steps of: providing a logic gate array having an input plane and output plane, said logic gate array including a plurality of logic gates, each gate having an input and an output in the input plane and the output plane, respectively; grouping said logic gates on said logic gate array into a series of N cells, each cell containing M logic gates; mapping the outputs of said logic gates of at least one of said cells onto the input plane of the array in cell-to-cell fashion such that all outputs of a cell-to-cell mapped cell are mapped onto the corresponding inputs of a respective predetermined cell; and mapping the outputs of the logic gates of at least one of said cells onto the input plane array in cell-shifted fashion so that only some of the outputs from a cell-shifted mapped cell are mapped onto the corresponding inputs of a respective predetermined cell, whereby a series of M similar interconnected logic modules are defined, each logic module comprising N logic gates and a set of connections between a plurality of logic gates within the module, said set of connections being the same for each module.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-04-24 | 1992-10-24 | 1993-04-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-04-24 | 1996-10-24 | 1997-04-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-04-24 | 2000-10-24 | 2001-04-25 | $7700.00 | Window Closed / Lapsed |