Memory device with comparison function

Claim 2

A memory device with a comparison function comprising: a plurality of unit cells connected in a matrix of rows and columns such that each row forms a memory word; each unit cell including: (a) a memory cell for holding data to be stored, said memory cell coupled to a bit line and a word line; (b) a sense input node connected to a sense output node of a less significant neighboring memory cell in the word; (c) a sense output node connected to a sense input node of a more significant neighboring memory cell in the word; (d) a first switching circuit disposed between one of said sense nodes and a first power supply terminal, and having two control inputs which receive the logical complement of the stored data in said memory cell and input data on said bit line, respectively, wherein said first switching circuit is conductive only when both control inputs are at a logical "1" level; (e) a second switching circuit disposed between said sense output node and said sense input node, and having two control inputs which receive the stored data in said memory cell and the logical complement of the input data on said bit line, respectively, wherein said second switching circuit is non-conductive only when both control inputs are at a logical "1" level; load elements respectively disposed between a second power supply terminal and the sense output node of the most significant MSB memory cell in each word; whereby, results of the comparison can be detected by the voltages across said load elements.

Claim 3

The memory device of claim 1, wherein in each unit cell, said memory cell is a memory cell of static random access memory.

Claim 4

The memory device of claim 1, wherein in each unit cell, said memory cell is coupled to a pair of bit lines to which complimentary signals are applied.

Claim 5

The memory device of claim 1, wherein in each unit cell, said first switching circuit is composed of two field effect transistors which are series-connected and the gate of one field effect transistor is connected to the bit line and the gate of the other field effect transistor is connected to the output of the memory cell.

Claim 6

The memory device of claim 1, wherein each of said load elements is composed of a field effect transistor.

Claim 7

The memory device of claim 1, wherein in each unit cell, said second switching circuit is composed of a parallel connection of two field effect transistors and the gate of one field effect transistor is connected to the output of the memory cell and the gate of the other field effect transistor is connected to the bit line.

Claim 8

The memory device of claim 1, wherein said first power supply terminal is ground.

Claim 9

The memory device of claim 1, wherein said second power supply terminal is a positive power supply terminal.

Claim 10

The memory device of claim 1, wherein in each unit cell, said second switching circuit is composed of a NAND circuit and a field effect transistor, and two input terminals of said NAND circuit are connected to the output of the memory cell, the bit line, respectively, and the output of the NAND circuit is connected to the gate of said field effect transistor, and the field effect transistor is disposed in said sence line.

Claim 11

The memory device of claim 9, wherein in each unit cell, said NAND circuit is composed of three field effect transistors connected is series.

Claim 12

The memory device of claim 1, wherein an amplifier is inserted into approximately the center of each row of unit cells for amplifying the signal to be propagated on said sense line.

Claim 13

The memory device of claim 11, wherein said amplifier is composed of a field effect transistor and an inverter, the output of which which is connected to the gate of the field effect transistor.

Claim 14

A memory device with a comparison function comprising: a plurality of unit cells connected in matrix of rows and columns such that each row forms a memory word; each unit cell including: (a) a memory cell for holding data to be stored, said memory cell having a bit line and a word line; (b) a sense input node wherein a sense output of an LSB neighboring memory cell on the word is connected; (c) a sense output node connected to a sense input node of an MSB neighboring memory cell on the word; (d) a first switching circuit with two control inputs, which is disposed between said sense input node or output node and a first power supply terminal, whose control inputs receive the logical complement of the stored data in said memory cell and input data on said bit line, respectively, wherein said first switching circuit is conductive only when both control inputs are at a logical "1" level; (e) a second switching circuit with two control inputs, which is disposed between said sense output node and said sense input node, whose control inputs receive the stored data in said memory cell and logical complement of the input data on said bit line, respectively, wherein said second switching circuit is non-conductive only when both control inputs are at a logical "1" level; load elements disposed between a second power supply and said sense output nodes of MSB memory cells in each word; whereby, results of the comparison can be detected by the voltages across said load elements; wherein said memory cells each comprise static random access memory cells; and wherein said second switching circuit is composed of a NAND circuit and a field effect transistor whose current path is connected between said sense input node and said sense output node, wherein two input terminals of said NAND circuit are connected to an output of the memory cell and said bit line, respectively, and an output of the NAND circuit is connected to a gate of said field effect transistor.

Claim 15

A memory device with a comparison function comprising: a plurality of unit cells connected in matrix of rows and columns such that each row forms a memory word; each unit cell including: (a) a memory cell for holding data to be stored, said memory cell having a bit line and a word line; (b) a sense input node wherein a sense output of an LSB neighboring memory cell on the word is connected; (c) a sense output node connected to a sense input node of an MSB neighboring memory cell on the word; (d) a first switching circuit with two control inputs, which is disposed between said sense input node or output node and a first power supply terminal, whose control inputs receive the logical complement of the stored data in said memory cell and input data on said bit line, respectively, wherein said first switching circuit is conductive only when both control inputs are at a logical "1" level; (e) a second switching circuit with two control inputs, which is disposed between said sense output node and said sense input node, whose control inputs receive the stored data in said memory cell and logical complement of the input data on said bit line, respectively, wherein said second switching circuit is non-conductive only when both control inputs are at a logical "1" level; load elements disposed between a second power supply and said sense output nodes of MSB memory cells in each word; whereby, results of the comparison can be detected by the voltages across said load elements; wherein said memory cells each comprise static random access memory cells; and wherein said second switching circuit is composed of a NAND circuit and a field effect transistor whose current path is connected between said sense input node and said sense output node, wherein two input terminals of said NAND circuit are connected to an output of the memory cell and said bit line, respectively, and an output of the NAND circuit is connected to a gate of said field effect transistor.