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US4823130A
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Method and control system for generating a variable output bit analog to digital converter
Assignee: Siemens Automotive LP
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Filing: 1988-02-18
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Granted: 1989-04-18
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Expires: 2008-02-18
Abstract
Abstract In a digital control system wherein control voltages are analog voltages, a method and control system for generating a variable output bit resolution from an N bit analog to digital converter utilizing a control circuit to control the input spread of the voltage references to the A/D converter. Depending on the binary value of the MSD position, the input reference voltage spread is controlled. If the binary value is zero, the input reference voltage spread is one-half the normal value and the resolution is N+1 bits and if the binary value is zero for both the MSD and MSD-1 positions, the input reference voltage spread is one-fourth the normal value and the resolution is N+2 bits and so on until the first binary one value is found after consecutive preceding binary zero values.
Inventors
- 👤 Danny O. Wright
- 👤 Kregg S. Wiggins
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 04:06
CPC Classifications
H; H03; H03M; H03M1/00; H03M1/12; H03M1/14; H03M1/16; H03M1/004; H03M1/007
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
182 words
A method for generating a variable output bit resolution from an N bit analog to digital converter comprising the steps of: reading the analog voltage to be converted; converting a first time in an analog to digital converter said analog voltage into an N bit digital word; testing the most significant bit position of the N bit digital word for a binary zero value; responding to a binary zero value in said most significant bit position for testing the binary value of each preceding consecutive significant bit position for a binary zero value until the first binary one value; responding to said binary one value for shifting the high input voltage reference to said analog to digital converter to a value equal to 2 -X its original value, wherein X equals the number of consecutive zero bit positions starting from the most significant bit position and proceeding toward the least significant bit position until said first binary one value; and then converting a second and final time in an analog to digital converter said analog voltage into an N+X bit digital word.
Claim 2
Independent Claim
182 words
A method for generating a variable output bit resolution from an N bit analog to digital converter comprising the steps of: reading the analog voltage to be converted; converting a first time in an analog to digital converter said analog voltage into an N bit digital word; testing the most significant bit position of the N bit digital word for a binary zero value; responding to a binary zero value in said most significant bit position for testing the binary value of each preceding consecutive significant bit position for a binary zero value until the first binary one value; responding to said binary one value for shifting the high input voltage reference to said analog to digital converter to a value equal to 2 -X its original value, wherein X equals the number of consecutive zero bit positions starting from the most significant bit position and proceeding toward the least significant bit position until said first binary one value; and then converting a second and final time in an analog to digital converter said analog voltage into an N+X bit digital word.
Claim 3
Dependent Claim
224 words
A control system for generating a variable output bit resolution from an N bit analog to digital converter comprising: means for generating an analog signal; means for generating a first pair of voltage references V REF and V REFL ; an N bit analog to digital converter having at least one input port for receiving said analog signal, at least two voltage reference ports for receiving said voltage references, and N output ports for generating an N bit digital word from said analog signal; means responsive to consecutive binary zero bit values preceding from the most significant bit position of said N bit digital word for generating said pair of voltage references to said voltage reference ports, wherein said pair of voltage references has a voltage spread wherein the new upper voltage level is: V.sub.REF new =(2.sup.-X)V.sub.REF original and the lower voltage level V REFL is zero voltage level for generating N+X bit resolution from said N bit analog to digital converter wherein X equals the number of consecutive binary zero bit values in said N bit digital word and means for converting said analog signal with said new upper voltage level to generate a digital output signal having a resolution equal to the basic number of bits of the converter plus additional bits equal to the number of consecutive binary zero bit values.
Claim 4
Dependent Claim
224 words
A control system for generating a variable output bit resolution from an N bit analog to digital converter comprising: means for generating an analog signal; means for generating a first pair of voltage references V REF and V REFL ; an N bit analog to digital converter having at least one input port for receiving said analog signal, at least two voltage reference ports for receiving said voltage references, and N output ports for generating an N bit digital word from said analog signal; means responsive to consecutive binary zero bit values preceding from the most significant bit position of said N bit digital word for generating said pair of voltage references to said voltage reference ports, wherein said pair of voltage references has a voltage spread wherein the new upper voltage level is: V.sub.REF new =(2.sup.-X)V.sub.REF original and the lower voltage level V REFL is zero voltage level for generating N+X bit resolution from said N bit analog to digital converter wherein X equals the number of consecutive binary zero bit values in said N bit digital word and means for converting said analog signal with said new upper voltage level to generate a digital output signal having a resolution equal to the basic number of bits of the converter plus additional bits equal to the number of consecutive binary zero bit values.
Claim 5
Dependent Claim
83 words
In the control system according to claim 2 additionally including means responsive to consecutive binary one bit values from the most significant bit position for generating a pair of voltage references to said voltage reference ports, wherein said new pair of voltage references having a voltage spread wherein the new lower voltage level is: V.sub.REFL new =(1-2.sup.-X)V.sub.REFL original and the upper voltage level V REFH is the original voltage level for generating N+X bit resolution from said N bit analog to digital converter.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-04-17 | 1992-10-17 | 1993-04-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-04-17 | 1996-10-17 | 1997-04-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-04-17 | 2000-10-17 | 2001-04-18 | $7700.00 | Window Closed / Lapsed |