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US4821231A Expired / Lapsed US ⏱️ 0.0 years remaining

Method and apparatus for selectively evaluating an effective address for a coprocessor

Assignee: NXP USA Inc
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Filing: 1987-12-21
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Granted: 1989-04-11
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Expires: 2007-12-21
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Abstract

Abstract A system for interfacing a Processor to a Coprocessor using standard bus cycles. The Processor, upon encountering in its instruction stream an instruction having a particular Operation word format, will transfer a Command word following the Operation word to a particular Coprocessor designated by a Coprocessor Identity field in the Operation word, Upon decoding the Command word, the Coprocessor will respond with any of a set of response primitives whcih define functions which the Coprocessor requires to Processor to perform in support of the Command by the Coprocessor. The interface provides for all functions which the Coprocessor may require, including selective vectoring to appropriate exception handlers.

Inventors

  • 👤 Michael Cruess
  • 👤 David Mothersole
  • 👤 John Zolnowsky
  • 👤 Douglas B. MacGregor

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-07 10:35
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3861; G06F9/3877; G06F9/3879; G06F9/3881

Claims Analysis

Total Claims: 2
Claim 1
Independent Claim 213 words
In a coprocessing data processing system, a method for selectively changing the flow of the instruction stream of a first data processor from a second data processor, comprising the steps of: receiving a predetermined instruction for execution by the first data processor; providing to the second data processor from the first data processor an indication that the predetermined instruction has been received for execution by the first data processor; receiving from the second data processor a response to the indication provided by the first data processor, the response indicating how the flow of the instruction stream of the first data processor is to be changed; and changing the flow of the instruction stream of the first data processor in accordance with the response received from the second data processor wherein the flow of the instruction stream of the first data processor is controlled by the value of a program counter; wherein the response received by the second data processor indicates a selected value to be loaded into the program counter; and wherein the step of changing the flow of the instruction stream of the first data processor is further characterized as loading into the program counter of the first data processor the value indicated by the response received from the second data processor.
Claim 2
Dependent Claim 213 words
In a coprocessing data processing system, a method for selectively changing the flow of the instruction stream of a first data processor from a second data processor, comprising the steps of: receiving a predetermined instruction for execution by the first data processor; providing to the second data processor from the first data processor an indication that the predetermined instruction has been received for execution by the first data processor; receiving from the second data processor a response to the indication provided by the first data processor, the response indicating how the flow of the instruction stream of the first data processor is to be changed; and changing the flow of the instruction stream of the first data processor in accordance with the response received from the second data processor wherein the flow of the instruction stream of the first data processor is controlled by the value of a program counter; wherein the response received by the second data processor indicates a selected value to be loaded into the program counter; and wherein the step of changing the flow of the instruction stream of the first data processor is further characterized as loading into the program counter of the first data processor the value indicated by the response received from the second data processor.

References Cited (Backward Citations)

US3614745A Cited
US3678467A Cited
US3871578A Cited
US3970993A Cited
US4149240A Cited
US4101960A Cited
US4270167A Cited
US4509116A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1992-04-10 1992-10-10 1993-04-11 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1996-04-10 1996-10-10 1997-04-11 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2000-04-10 2000-10-10 2001-04-11 $7700.00 Window Closed / Lapsed

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