Junction field effect transistor

Claim 2

A junction field effect semiconductor device comprising: a semiconductor substrate, a first semiconductor layer of a first conductivity type, formed on said substrate, source and drain semiconductor regions of a second conductivity type opposite to said first conductivity type, formed in said first semiconductor layer, said source and drain regions being separated from each other, each of said source and drain regions extending from a first end to a second end, a channel semiconductor layer of said second conductivity type, formed only in an area bounded by a quadrangle having two opposite sides one of which joins said first and second ends of said source region, and the other of which joins said first and second ends of said drain region, a highly doped gate semiconductor region of said first conductivity type, surrounding said source region, said drain region and said channel layer, said gate region being separated from said channel layer by said first layer, and having an impurity concentration higher than that of said first layer, a highly doped gate semiconductor layer of said first conductivity type, formed on said channel layer, said gate layer covering substantially an entire upper surface of said channel layer and extending beyond said channel layer and reaching said gate region, and an oxide layer formed on said gate layer above said channel layer, and a metal electrode formed on said oxide layer and separated from said gate layer and said channel layer by said oxide layer.

Claim 3

A semiconductor device as claimed in claim 1 wherein each of said source and drain regions extends from said first end to said second end in parallel to the other so that a rectangle is formed by said first and second ends of said source and drain regions, and said channel layer is formed only within an area bounded by said rectangle.

Claim 4

A semiconductor device as claimed in claim 2 wherein said first conductivity type is an n-type, and said second conductivity type is a p-type.

Claim 5

A semiconductor device as claimed in claim 3 wherein a width of said channel layer is smaller than a length between said first and second ends of said source and drain regions.

Claim 6

A semiconductor device as claimed in claim 4 wherein said channel layer has a source end in contact with said source region, a drain end in contact with said drain region, and first and second sides joining said source and drain ends of said channel layer, said first and second sides being separated from said gate region and in contact with said first semiconductor layer.

Claim 7

A semiconductor device as claimed in claim 5 wherein said source and drain regions and said channel layer are surrounded by a peripheral area in which said gate layer is formed directly on said first semiconductor layer.

Claim 8

A junction field effect semiconductor device comprising: a semiconductor substrate, a first semiconductor layer of a first conductivity type, formed on said substrate, source and drain semiconductor regions of a second conductivity type opposite to said first conductivity type, formed in said first semiconductor layer, said source and drain regions being separated from each other, each of said source and drain regions extending from a first end to a second end, a channel semiconductor layer of said second conductivity type, formed only in an area bounded by a quadrangle having two opposite sides one of which joins said first and second ends of said source region, and the other of which joins said first and second ends of said drain region, a highly doped gate semiconductor region of said first conductivity type, surrounding said source region, said drain region and said channel layer, said gate region being separated from said channel layer by said first layer, and having an impurity concentration higher than that of said first layer, a highly doped gate semiconductor layer of said first conductivity type, formed on said channel layer, said gate layer covering substantially an entire upper surface of said channel layer and extending beyond said channel layer and reaching said gate region, an oxide layer formed on said gate layer above said channel layer, and a metal electrode formed on said oxide layer and separated from said gate layer and said channel layer by said oxide layer, and said electrode is electrically connected to said gate region so as to make a potential of said electrode equal to a potential of said gate region.

Claim 9

A junction field effect semiconductor device comprising: a semiconductor substrate, a first semiconductor layer of a first conductivity type, formed on said substrate, source and drain semiconductor regions of a second conductivity type opposite to said first conductivity type, formed in said first semiconductor layer, said source and drain regions being separated from each other, each of said source and drain regions extending from a first end to a second end, a channel semiconductor layer of said second conductivity type, formed only in an area bounded by a quadrangle having two opposite sides one of which joins said first and second ends of said source region, and the other of which joins said first and second ends of said drain region, a highly doped gate semiconductor region of said first conductivity type, surrounding said source region, said drain region and said channel layer, said gate region being separated from said channel layer by said first layer, and having an impurity concentration higher than that of said first layer, a highly doped gate semiconductor layer of said first conductivity type, formed on said channel layer, said gate layer covering substantially an entire upper surface of said channel layer and extending beyond said channel layer and reaching said gate region, an oxide layer formed on said gate layer above said channel layer, and a metal electrode formed on said oxide layer and separated from said gate layer and said channel layer by said oxide layer, and said electrode is electrically connected to said gate region so as to make a potential of said electrode equal to a potential of said gate region.

Claim 10

A semiconductor device according to claim 1 wherein each of said channel layers and said highly doped gate layer are layers formed by ion implantation.