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US4816722A
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Digital phase-locked loop filter
Assignee: Ricoh Co Ltd
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Filing: 1987-12-16
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Granted: 1989-03-28
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Expires: 2007-12-16
Abstract
Abstract A phase-locked loop filter applicable to a motor speed control of an optical disk apparatus and others counts a difference in phase between an input signal to a phase-locked loop and an output signal of the loop, integrates the resulting counts modulo a predetermined value which is dependent upon the period of a clock, produces an overflow signal every time an overflow occurs, and generates the output signal by dividing the frequency of the overflow signal.
Inventors
- 👤 Toshihiro Shigemori
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 15:43
CPC Classifications
G; G11; G11B; G11B19/00; G11B19/20; G11B19/28; H; H03; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/099; H03L7/0991; H03L7/0994; Y; Y10; Y10S; Y10S388/00; Y10S388/907; Y10S388/911; Y10S388/912
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
95 words
A digital phase-locked loop filter having at least one phase-locked loop, said phase-locked loop comprising: counter means supplied with an input signal and an output signal for counting a difference in phase between said input and output signals and producing a resulting count; integrator means supplied with said count and a clock signal for integrating said counts modulo a predetermined value at a period of said clock signal and, every time an overflow occurs, producing an overflow signal; and frequency divider means for generating said output signal by dividing a frequency of said overflow signal.
Claim 2
Dependent Claim
95 words
A digital phase-locked loop filter having at least one phase-locked loop, said phase-locked loop comprising: counter means supplied with an input signal and an output signal for counting a difference in phase between said input and output signals and producing a resulting count; integrator means supplied with said count and a clock signal for integrating said counts modulo a predetermined value at a period of said clock signal and, every time an overflow occurs, producing an overflow signal; and frequency divider means for generating said output signal by dividing a frequency of said overflow signal.
Claim 3
Dependent Claim
24 words
A digital phase-locked loop filter as claimed in claim 1, wherein said counter means and said integrator means each has more than one bit.
Claim 4
Dependent Claim
34 words
A digital phase-locked loop filter as claimed in claim 2, wherein said counter means comprises an up-down counter which up-counts in response to said input signal and down-counts in response to said output signal.
Claim 5
Dependent Claim
40 words
A digital phase-locked loop filter as claimed in claim 3, wherein said integrator means comprises a latch supplied with said clock signal, and an adder supplied with said counts and an output of said latch for producing said overflow signal.
Claim 6
Dependent Claim
84 words
A digital phase-locked loop filter as claimed in claim 1, wherein said counter means comprises an edge detector for detecting a positive-going edge of said input signal and producing a single up-counting signal per period of said input signal, and an up-down counter up-counting in response to said up-count signal and down-counting in response to a down-count signal outputted by said frequency divider for comparing a phase of said input signal and a phase of said output signal to thereby determine said phase difference.
Claim 7
Dependent Claim
55 words
A digital phase-locked loop filter as claimed in claim 5, wherein said integrator means comprises an adder integrating said counts modulo said predetermined value and producing a resulting sum, and a latch supplied with a clock signal for reading in said sum of said adder while feeding an output of said latch to said adder.
Claim 8
Dependent Claim
41 words
A digital phase-locked loop filter as claimed in claim 6, wherein said frequency divider means comprises a frequency converter which generates said output signal by dividing said overflow signal and produces said down-count signal once per period of said output signal.
Claim 9
Independent Claim
109 words
A device for controlling rotation speed of a motor, comprising: speed sensor means for producing two speed signals by sensing a rotation speed of said motor; edge detector and combiner means for detecting positive-going edges of said speed signals and combining said two signals such that said signals do not overlap each other with respect to a time axis; a phase-locked loop filter supplied with said combined signal for producing a single output signal having a frequency which is proportional to the rotation speed of said motor; and control means responsive to said output signal of said filter for controlling drive of said motor and, thereby, the rotation speed.
Claim 10
Independent Claim
109 words
A device for controlling rotation speed of a motor, comprising: speed sensor means for producing two speed signals by sensing a rotation speed of said motor; edge detector and combiner means for detecting positive-going edges of said speed signals and combining said two signals such that said signals do not overlap each other with respect to a time axis; a phase-locked loop filter supplied with said combined signal for producing a single output signal having a frequency which is proportional to the rotation speed of said motor; and control means responsive to said output signal of said filter for controlling drive of said motor and, thereby, the rotation speed.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-03-27 | 1992-09-26 | 1993-03-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-03-27 | 1996-09-26 | 1997-03-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-03-27 | 2000-09-26 | 2001-03-28 | $7700.00 | Window Closed / Lapsed |