Patent US4816702A successfully refreshed from Google Patents.
US4816702A
Expired / Lapsed
US
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CMOS logic circuit
Assignee: STMicroelectronics SRL
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Filing: 1987-12-09
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Granted: 1989-03-28
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Expires: 2007-12-09
Abstract
Abstract A CMOS logic circuit for sampling data coming from TTL logic circuits under frequency control by a system's clock intrinsically faster than prior art similar circuits is obtained by combining a TTL/CMOS compatibility interface inverting stage with a first stage of the sampling circuit (master or latch stage). The circuit of the invention permits elimination of two inverters and therefore reduction of data transfer delay.
Inventors
- 👤 Alberto Salina
- 👤 Domenico Rossi
- 👤 Claudio Diazzi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 22:21
CPC Classifications
H; H03; H03K; H03K3/00; H03K3/02; H03K3/353; H03K3/356; H03K3/3565; H03K3/027; H03K3/037; H03K3/0372
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
173 words
In a CMOS circuit having a logic circuit for directly sampling data transmitted from TTL logic circuits under frequency control of a system clock, the data having logic states of "0" and "1," the logic circuit comprising: a first switch for accepting the data; a TTL/CMOS compatibility interface stage having an input connected to the output of the first switch; an inverter stage having an input connected to the output of the TTL/CMOS compatibility interface stage; a second switch having an input connected to the output of the inverter stage, the output of the second switch being connected to the input of the TTL/CMOS compatibility interface stage to effect a feedback for the TTL/CMOS compatibility interface stage; wherein the first and second switches are controlled synchronously and in opposite phases in accordance with clock pulses generated by the clock to remove the need to have an input interface circuit connected thereto in order to sample data transmitted from the TTL logic circuits; whereby time delays introduced by the input interface circuit are eliminated.
Claim 2
Dependent Claim
173 words
In a CMOS circuit having a logic circuit for directly sampling data transmitted from TTL logic circuits under frequency control of a system clock, the data having logic states of "0" and "1," the logic circuit comprising: a first switch for accepting the data; a TTL/CMOS compatibility interface stage having an input connected to the output of the first switch; an inverter stage having an input connected to the output of the TTL/CMOS compatibility interface stage; a second switch having an input connected to the output of the inverter stage, the output of the second switch being connected to the input of the TTL/CMOS compatibility interface stage to effect a feedback for the TTL/CMOS compatibility interface stage; wherein the first and second switches are controlled synchronously and in opposite phases in accordance with clock pulses generated by the clock to remove the need to have an input interface circuit connected thereto in order to sample data transmitted from the TTL logic circuits; whereby time delays introduced by the input interface circuit are eliminated.
Claim 3
Dependent Claim
45 words
The logic circuit according to claim 1 wherein the TTL/CMOS compatibility interface stage is a Schmidt trigger circuit; and wherein the inverter stage connected to the TTL/CMOS compatibility interface stage is used to reset the phase of signals outputted from the TTL/CMOS compatibility interface stage.
Claim 4
Dependent Claim
45 words
The logic circuit according to claim 1, wherein the TTL/CMOS compatibility interface stage is a hysteresis comparator circuit; and wherein the inventer stage connected to the TTL/CMOS compatibility interface stage is used to reset the phase of signals outputted from the TTL/CMOS compatibility interface stage.
Claim 5
Dependent Claim
91 words
The logic circuit according to claim 1, further comprising: a third switch having an input connected to the output of the TTL/CMOS compatibility interface stage; a second inverter stage having an input connected to the output of the third switch; wherein the output of the second inverter stage is connected to its own input through a third inverter stage and a fourth switch; and wherein the third and fourth switches are controlled synchronously and in opposite phases, and with respect to the first and second switches, by the generated clock pulses.
Claim 6
Dependent Claim
91 words
The logic circuit according to claim 2, further comprising: a third switch having an input connected to the output of the TTL/CMOS compatibility interface stage; a second inverter stage having an input connected to the output of the third switch; wherein the output of the second inverter stage is connected to its own input through a third inverter stage and a fourth switch; and wherein the third and fourth switches are controlled synchronously and in opposite phases, and with respect to the first and second switches, by the generated clock pulses.
Claim 7
Dependent Claim
91 words
The logic circuit according to claim 3, further comprising: a third switch having an input connected to the output of the TTL/CMOS compatibility interface stage; a second inverter stage having an input connected to the output of the third switch; wherein the output of the second inverter stage is connected to its own input through a third inverter stage and a fourth switch; and wherein the third and fourth switches are controlled synchronously and in opposite phases, and with respect to the first and second switches, by the generated clock pulses.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-03-27 | 1992-09-26 | 1993-03-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-03-27 | 1996-09-26 | 1997-03-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-03-27 | 2000-09-26 | 2001-03-28 | $7700.00 | Window Closed / Lapsed |