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US4815112A
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Read-only sequence control system
Assignee: Individual
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Filing: 1987-06-02
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Granted: 1989-03-21
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Expires: 2007-06-02
Abstract
Abstract A read-only sequence control system comprises a control unit having counters for determining the cycle time of the system and timing for the performance of various operations an EPROM and a plurality of relays responsive to data outputs of the EPROM for controlling a machine. The system has a first sensor for detecting the entrance of a work part into the machine and a second sensor for detecting discharge of the entered work part. When the second sensor does not detect the work at an end of working cycle, the control unit operates to stop the machine.
Inventors
- 👤 Yoshikazu Kuze
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 18:07
CPC Classifications
G; G05; G05B; G05B19/00; G05B19/02; G05B19/04; G05B19/045
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
118 words
A read-only sequence control system for controlling the operation of a machine, having a memory, a control unit including a clock pulse generating circuit for producing clock pulses, a presettable counter for counting the clock pulses, and for producing a read clock pulse after every preset count has been reached, a binary counter for counting the read clock pulse and for producing outputs for addressing said memory, so that the memory produces data outputs to turn on relays for operating the machine, and a control circuit for controlling start and stop operations of the counters, the control system comprising: a first sensor detecting a feed of a work part into the machine and for producing a feed signal;
Claim 2
Dependent Claim
118 words
A read-only sequence control system for controlling the operation of a machine, having a memory, a control unit including a clock pulse generating circuit for producing clock pulses, a presettable counter for counting the clock pulses, and for producing a read clock pulse after every preset count has been reached, a binary counter for counting the read clock pulse and for producing outputs for addressing said memory, so that the memory produces data outputs to turn on relays for operating the machine, and a control circuit for controlling start and stop operations of the counters, the control system comprising: a first sensor detecting a feed of a work part into the machine and for producing a feed signal;
Claim 3
Dependent Claim
122 words
a first flip-flop responsive to said feed signal for operating said clock pulse generating circuit, presettable counter, and binary counter; first gate means responsive to a count end signal of said binary counter for producing a stop signal for stopping the production of said read clock pulse from the presettable counter; second gate means opened by the count end signal; a second sensor detecting a discharge of the fed work part and for producing a discharge signal to close said second gate means; first circuit means responsive to an absence of said discharge signal for keeping the second gate means open to produce an abnormality signal; and second circuit means responsive to the abnormality signal for stopping operation of the presettable counter.
Claim 4
Dependent Claim
122 words
a first flip-flop responsive to said feed signal for operating said clock pulse generating circuit, presettable counter, and binary counter; first gate means responsive to a count end signal of said binary counter for producing a stop signal for stopping the production of said read clock pulse from the presettable counter; second gate means opened by the count end signal; a second sensor detecting a discharge of the fed work part and for producing a discharge signal to close said second gate means; first circuit means responsive to an absence of said discharge signal for keeping the second gate means open to produce an abnormality signal; and second circuit means responsive to the abnormality signal for stopping operation of the presettable counter.
Claim 5
Dependent Claim
37 words
The sequence control system according to claim 1 wherein the second gate means includes a second flip-flop responsive to the count end signal for producing a gate signal and a logic gate opened by said gate signal.
Claim 6
Dependent Claim
35 words
The sequence control system according to claim 2 wherein the first circuit means includes means responsive to the discharge signal for operating the second flip-flop to invert the logic gate signal to close the gate.
Claim 7
Dependent Claim
24 words
The sequence control system according to claim 3 wherein the logic gate is further responsive to said feed signal to produce the abnormality signal.
Claim 8
Dependent Claim
41 words
The sequence control system according to claim 1 further comprising a terminal for connecting to another control system so as to apply an output of the second circuit means of said another control system to stop operation of said presettable counter.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-03-20 | 1992-09-19 | 1993-03-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-03-20 | 1996-09-19 | 1997-03-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-03-20 | 2000-09-19 | 2001-03-21 | $7700.00 | Window Closed / Lapsed |