US4815041A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Current surge elimination for CMOS devices
Assignee: Nokia Bell Labs
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Filing: 1987-03-19
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Granted: 1989-03-21
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Expires: 2007-03-19
Abstract
Abstract A possible surge current which can develop during power initialization of CMOS circuit arrangements or at other instances, because of loss of an actual clock signal, is eliminated by controllably supplying an alternate clock signal to the CMOS devices in the circuit during intervals in which the actual clock signal is absent. The presence or absence of the actual clock signal is monitored continuously and when present, the actual clock signal is controllably supplied to the CMOS devices in place of the alternate clock signal.
Inventors
- 👤 Gerald A. Baylock
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 18:25
CPC Classifications
H; H02; H02H; H02H9/00; H02H9/02; H03; H03K; H03K19/00; H03K19/003; H03K19/00315; H03K19/0008; H03K19/0016; H03K19/00346; H03K19/00361; H03K5/00
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
267 words
Apparatus including at least one CMOS device adapted to be connected to a power source and adapted to be supplied with at least one actual clock signal, comprising: means for detecting the absence of the at least one actual clock signal, said means for detecting includes means for detecting a first interval that the at least one actual clock signal is in a first predetermined state and a second interval that the at least one actual clock signal is in a second predetermined state, means for comparing said first interval to a first predetermined threshold interval and means for comparing said second interval to a second predetermined threshold interval, said means for detecting generates a control signal having a first predetermined state when said first interval is longer than said first threshold interval or when said second interval is longer than said second threshold interval indicating that said at least one actual clock signal is absent and a second predetermined state of said control signal otherwise indicating that said at least one actual clock signal is present; and means for controllably supplying at least one alternate clock signal to said at least one CMOS device during intervals in which said at least one actual clock signal is absent, said means for controllably supplying includes controllable switching means responsive to said first state of said control signal for supplying said at least one alternate clock signal to said at least one CMOS device and to said second state of said control signal for supplying the at least one actual clock signal to said at least one CMOS device.
Claim 2
Dependent Claim
267 words
Apparatus including at least one CMOS device adapted to be connected to a power source and adapted to be supplied with at least one actual clock signal, comprising: means for detecting the absence of the at least one actual clock signal, said means for detecting includes means for detecting a first interval that the at least one actual clock signal is in a first predetermined state and a second interval that the at least one actual clock signal is in a second predetermined state, means for comparing said first interval to a first predetermined threshold interval and means for comparing said second interval to a second predetermined threshold interval, said means for detecting generates a control signal having a first predetermined state when said first interval is longer than said first threshold interval or when said second interval is longer than said second threshold interval indicating that said at least one actual clock signal is absent and a second predetermined state of said control signal otherwise indicating that said at least one actual clock signal is present; and means for controllably supplying at least one alternate clock signal to said at least one CMOS device during intervals in which said at least one actual clock signal is absent, said means for controllably supplying includes controllable switching means responsive to said first state of said control signal for supplying said at least one alternate clock signal to said at least one CMOS device and to said second state of said control signal for supplying the at least one actual clock signal to said at least one CMOS device.
Claim 3
Dependent Claim
16 words
The apparatus as defined in claim 1 wherein said first and second threshold intervals are equal.
Claim 4
Dependent Claim
32 words
The apparatus as defined in claim 2 further including a source of the at least one actual clock signal, the at least one actual clock signal having a predetermined magnitude and frequency.
Claim 5
Dependent Claim
44 words
The apparatus as defined in claim 3 further including a source of said at least one alternate clock signal, said at least one alternate clock signal having a prescribed magnitude and a frequency approximately equal to the at least one actual clock signal frequency.
Claim 6
Dependent Claim
279 words
Apparatus including a plurality of CMOS devices adapted to be connected to a power source and adapted to be supplied with at least one clock signal, comprising: a source of at least one actual clock signal; a source of at least one alternate clock signal; means for detecting the absence of said at least one actual clock signal, said means for detecting includes means for detecting a first interval that said at least one actual clock signal is in a first predetermined state and a second interval that said at least one actual clock signal is in a second predetermined state, means for comparing said first interval to a first predetermined threshold interval and means for comparing said second interval to a second predetermined threshold interval, said means for detecting generates a control signal having a first predetermined state when said first interval is longer than said first threshold interval or when said second interval is longer than said second threshold interval indicating that said at least one actual clock signal is absent and a second predetermined state of said control signal otherwise indicating that said at least one actual clock signal is present; and means for controllably supplying said at least one alternate clock signal to the plurality of CMOS devices when said at least one actual clock signal is absent, said means for controllably supplying includes controllable switching means responsive to said first state of said control signal for supplying said at least one alternative clock signal to the plurality of CMOS devices and to said second state of said control signal for supplying said at least one actual clock signal to the plurality of CMOS devices.
Claim 7
Dependent Claim
279 words
Apparatus including a plurality of CMOS devices adapted to be connected to a power source and adapted to be supplied with at least one clock signal, comprising: a source of at least one actual clock signal; a source of at least one alternate clock signal; means for detecting the absence of said at least one actual clock signal, said means for detecting includes means for detecting a first interval that said at least one actual clock signal is in a first predetermined state and a second interval that said at least one actual clock signal is in a second predetermined state, means for comparing said first interval to a first predetermined threshold interval and means for comparing said second interval to a second predetermined threshold interval, said means for detecting generates a control signal having a first predetermined state when said first interval is longer than said first threshold interval or when said second interval is longer than said second threshold interval indicating that said at least one actual clock signal is absent and a second predetermined state of said control signal otherwise indicating that said at least one actual clock signal is present; and means for controllably supplying said at least one alternate clock signal to the plurality of CMOS devices when said at least one actual clock signal is absent, said means for controllably supplying includes controllable switching means responsive to said first state of said control signal for supplying said at least one alternative clock signal to the plurality of CMOS devices and to said second state of said control signal for supplying said at least one actual clock signal to the plurality of CMOS devices.
Claim 8
Dependent Claim
16 words
The apparatus as defined in claim 5 wherein said first and second threshold intervals are equal.
Claim 9
Dependent Claim
48 words
The apparatus as defined in claim 6 where said at least one actual clock signal has a predetermined magnitude and frequency and wherein said at least one alternate clock signal has a predetermined magnitude and a frequency approximately equal to said at least one actual clock signal frequency.
Claim 10
Dependent Claim
20 words
The apparatus as defined in claim 7 wherein said plurality of CMOS devices is on at least one VLSI chip.
Claim 11
Dependent Claim
210 words
A surge current elimination method for at least one CMOS device adapted to be connected to a power source and to be supplied with at least one actual clock signal, comprising the steps of, detecting a first interval that the at least one actual clock signal is in a first predetermined state and a second interval that the at least one actual clock signal is in a second predetermined state, comparing said first interval to a first predetermined threshold interval, comparing said second interval to a second predetermined threshold interval, generating a control signal having a first predetermined state when said first interval is longer than said first threshold interval or when said second interval is longer than said second threshold interval indicating that said at least one actual clock signal is absent and a second predetermined state of said control signal otherwise indicating that said at least one control signal is present, and controllably supplying at least one alternate clock signal to said at least one CMOS device during intervals that said first state of said control signal is generated and controllably supplying said at least one actual clock signal to said at least one CMOS device during intervals that said second state of said control signal is generated.
Claim 12
Dependent Claim
210 words
A surge current elimination method for at least one CMOS device adapted to be connected to a power source and to be supplied with at least one actual clock signal, comprising the steps of, detecting a first interval that the at least one actual clock signal is in a first predetermined state and a second interval that the at least one actual clock signal is in a second predetermined state, comparing said first interval to a first predetermined threshold interval, comparing said second interval to a second predetermined threshold interval, generating a control signal having a first predetermined state when said first interval is longer than said first threshold interval or when said second interval is longer than said second threshold interval indicating that said at least one actual clock signal is absent and a second predetermined state of said control signal otherwise indicating that said at least one control signal is present, and controllably supplying at least one alternate clock signal to said at least one CMOS device during intervals that said first state of said control signal is generated and controllably supplying said at least one actual clock signal to said at least one CMOS device during intervals that said second state of said control signal is generated.
References Cited (Backward Citations)
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Cited
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Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-03-20 | 1992-09-19 | 1993-03-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-03-20 | 1996-09-19 | 1997-03-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-03-20 | 2000-09-19 | 2001-03-21 | $7700.00 | Window Closed / Lapsed |