Sync detection circuit

Claim 2

A sync detection circuit for detecting a standard signal which is a signal having V-sync signals with a predetermined repetition period, a non-standard signal which is a signal having V-sync signals with a repetition period other than said predetermined repetition period, and a signal absent condition which occurs when the broadcasting is finished, or when a television receiver is switched to a non-broadcasting channel, said sync detection circuit comprising: V-sync separation means for separating V-sync signals; first counter means for counting said predetermined repetition period in relation to the generation of each said V-sync signal and for producing a count-up signal upon counting said predetermined repetition period; phase comparing means for comparing the phase of said count-up signal with the phase of a V-sync signal and for producing a first level signal, representing the receipt of said standard signal, when the compared signals have the same phase, and a second level signal, representing the receipt of said non-standard signal, when the compared signals have different phase; V-sync signal detecting means for receiving said V-sync signals directly from said V-sync separation means, for detecting said signal absent condition and for producing a first level signal upon detection of said signal absent condition.

Claim 3

A sync detection circuit as claimed in claim 1, further comprising OR gate means for receiving signals from said phase comparing means and signals from said V-sync signal detecting means and for taking a logic OR between said signals, thereby producing a first level signal when at least one of said phase comparing means and said V-sync detecing means is producing a first level signal.

Claim 4

A sync detection circuit as claimed in claim 2, further comprising: H-sync separation means for separating H-sync signals; and automatic frequency control means for controlling a frequency of a horizontal deflection in accordance with a frequency of said H-sync signals, said automatic frequency control means being arranged to reduce the sensitivity thereof upon receipt of a first level signal from said OR gate means.

Claim 5

A sync detection circuit as claimed in claim 2, wherein said V-sync signal detecting means comprises: second counter means for counting a predetermined time period, which is greater than said predetermined repetition period, in relation to the generation of said V-sync signal and for producing a time-up signal upon counting said predetermined time period; and condition detecting means, which is connected to receive said time-up signal and said V-sync signal, for detecting said signal absent condition when no V-sync signal appears before said time-up signal is produced.

Claim 6

A sync detection circuit for detecting a standard signal which is a signal having V-sync signals with a predetermined repetition period, a non-standard signal which is a signal having V-sync signals with a repetition period other than said predetermined repetition period, and a signal absent condition which occurs when the broadcasting is finished, or when a television receiver is switched to a non-broadcasting channel, said sync detection circuit comprising: V-sync separation means for separating V-sync signals; first counter means for counting said predetermined repetition period in relation to the generation of each said V-sync signal and for producing a count-up signal upon counting said predetermined repetition period; phase comparing means for comparing the phase of said count-up signal with the phase of a v-sync signal and for producing a first level signal, representing the receipt of said standard signal, when the compared signals have the same phase, and a second level signal, representing the receipt of said non-standard signal, when the compared signals have different phase; second counter means for counting a predetermined time period, which is greater than said predetermined repetition period, in relation to the generation of said v-sync signal supplied directly from said V-sync separation means and for producing a time-up signal upon counting said predetermined time period; and condition detecting means, which is connected to receive said time-up signal and said V-sync signal supplied directly from said V-sync separation means, for detecting said signal absent condition when no V-sync signal appears before said time-up signal is produced.

Claim 7

A sync detection circuit for detecting a standard signal which is a signal having V-sync signals with a predetermined repetition period, a non-standard signal which is a signal having V-sync signals with a repetition period other than said predetermined repetition period, and a signal absent condition which occurs when the broadcasting is finished, or when a television receiver is switched to a non-broadcasting channel, said sync detection circuit comprising: V-sync separation means for separating V-sync signals; first counter means for counting said predetermined repetition period in relation to the generation of each said V-sync signal and for producing a count-up signal upon counting said predetermined repetition period; phase comparing means for comparing the phase of said count-up signal with the phase of a v-sync signal and for producing a first level signal, representing the receipt of said standard signal, when the compared signals have the same phase, and a second level signal, representing the receipt of said non-standard signal, when the compared signals have different phase; second counter means for counting a predetermined time period, which is greater than said predetermined repetition period, in relation to the generation of said v-sync signal supplied directly from said V-sync separation means and for producing a time-up signal upon counting said predetermined time period; and condition detecting means, which is connected to receive said time-up signal and said V-sync signal supplied directly from said V-sync separation means, for detecting said signal absent condition when no V-sync signal appears before said time-up signal is produced.

Claim 8

A sync detection circuit as claimed in claim 5, wherein said condition detecting means produces a first level signal upon detection of said signal absent condition, and a second level signal when a V-sync signal appears before said time-up signal is produced.

Claim 9

A sync detection circuit as claimed in claim 6, further comprising: OR gate means for receiving signals from said phase comparing means and signals from said condition detecting means and for producing a first level signal when at least one of said phase comparing means and said condition detecting means is producing a first level signal; H-sync separation means for separating H-sync signals; and automatic frequency control means for controlling a frequency of a horizontal deflection in accordance with a frequency of said H-sync signals, said automatic frequency control means being arranged to operate under a low sensitive mode upon receipt of a first level signal from said OR gate means, and o operate under a high sensitive mode upon receipt of a second level signal from said OR gate means.

Claim 10

A sync detection circuit for detecting a standard signal which is a signal having V-sync signals with a predetermined repetition period, a non-standard signal which is a signal having V-sync signals with a repetition period other than said predetermined repetition period, said sync detecting circuit comprising; V-sync separation means for separating v-sync signals; first counter means for counting said predetermined repetition period in relation to the generation of each said V-sync signal and for producing a count-up signal upon counting said predetermined repetition period; phase comparing means for comparing the phase of said count-up signal with the phase of a v-sync signal and for producing a first level signal, representing the receipt of said standard signal, when the compared signals have the same phase, and a second level signal, representing the receipt of said non-standard signal, when the compared signals have different phase; H-sync separation means for separating H-sync signals; and automatic frequency control means for controlling a frequency of horizontal deflection in accordance with a frequency of said H-sync signals, said automatic frequency control means being arranged to operate under a low sensitive mode upon receipt of said first level signal from said phase comparing means, and to operation under a high sensitive mode upon receipt of second level signal from said phase comparing means.

Claim 11

A sync detection circuit for detecting a standard signal which is a signal having V-sync signals with a predetermined repetition period, a non-standard signal which is a signal having V-sync signals with a repetition period other than said predetermined repetition period, said sync detecting circuit comprising; V-sync separation means for separating v-sync signals; first counter means for counting said predetermined repetition period in relation to the generation of each said V-sync signal and for producing a count-up signal upon counting said predetermined repetition period; phase comparing means for comparing the phase of said count-up signal with the phase of a v-sync signal and for producing a first level signal, representing the receipt of said standard signal, when the compared signals have the same phase, and a second level signal, representing the receipt of said non-standard signal, when the compared signals have different phase; H-sync separation means for separating H-sync signals; and automatic frequency control means for controlling a frequency of horizontal deflection in accordance with a frequency of said H-sync signals, said automatic frequency control means being arranged to operate under a low sensitive mode upon receipt of said first level signal from said phase comparing means, and to operation under a high sensitive mode upon receipt of second level signal from said phase comparing means.

Claim 12

A sync detection circuit for detecting a standard signal which is a signal having V-sync signals with a predetermined repetition period, a non-standard signal which is a signal having V-sync signals with a repetition period other than said predetermined repetition period, and a signal absent condition which occurs when the broadcasting is finished, or when a television receiver is switched to a non-broadcasting channel, said sync detection circuit comprising: V-sync separation means for separating V-sync signals; first counter means for counting said predetermined repetition period in relation to the generation of each said V-sync signal and for producing a count-up signal upon counting said predetermined repetition period; phase comparing means for comparing the phase of said count-up signal with the phase of a V-sync signal and for producing a first level signal, representing the receipt of said standard signal, when the compared signals have the same phase, and a second level signal, representing the receipt of said non-standard signal, when the compared signals have different phase; V-sync signal detecting means for detecting said signal absent condition and for producing a first level signal upon detection of said signal absent condition; and OR gate means for receiving signals from said phase comparing means and signals from said V-sync signal detecting means and for taking a logic OR between said signals, thereby producing a first level signal when at least one of said phase comparing means and said V-sync detecting means is producing a first level signal.

Claim 13

A sync detection circuit for detecting a standard signal which is a signal having V-sync signals with a predetermined repetition period, a non-standard signal which is a signal having V-sync signals with a repetition period other than said predetermined repetition period, and a signal absent condition which occurs when the broadcasting is finished, or when a television receiver is switched to a non-broadcasting channel, said sync detection circuit comprising: V-sync separation means for separating V-sync signals; first counter means for counting said predetermined repetition period in relation to the generation of each said V-sync signal and for producing a count-up signal upon counting said predetermined repetition period; phase comparing means for comparing the phase of said count-up signal with the phase of a V-sync signal and for producing a first level signal, representing the receipt of said standard signal, when the compared signals have the same phase, and a second level signal, representing the receipt of said non-standard signal, when the compared signals have different phase; V-sync signal detecting means for detecting said signal absent condition and for producing a first level signal upon detection of said signal absent condition; and OR gate means for receiving signals from said phase comparing means and signals from said V-sync signal detecting means and for taking a logic OR between said signals, thereby producing a first level signal when at least one of said phase comparing means and said V-sync detecting means is producing a first level signal.

Claim 14

A sync detection circuit as claimed in claim 9, further comprising: H-sync separation means for separating H-sync signals; and automatic frequency control means for controlling a frequency of a horizontal deflection in accordance with a frequency of said H-sync signals, said automatic frequency control means being arranged to reduce the sensitivity thereof upon receipt of a first level signal from said OR gate means.

Claim 15

A sync detection circuit as claimed in claim 9, wherein said V-sync detecting means comprises: second counter means for counting a predetermined time period, which is greater than said predetermined repetition period, in relation to the generation of said V-sync signal and for producing a time-up signal upon counting said predetermined time period; and condition detecting means, which is connected to receive said time-up signal and said V-sync signal, for detecting said signal absent condition when no V-sync signal appears before said time-up signal is produced.

Claim 16

A sync detection circuit for detecting a standard signal which is a signal having V-sync signals with a predetermined repetition period, a non-standard signal which is a signal having V-sync signals with a repetition period other than said predetermined repetition period, and a signal absent condition which occurs when the broadcasting is finished, or when a television receiver is switched to a non-broadcasting channel, said sync detection circuit comprising: V-sync separation means for separating V-sync signals; first counter means for counting said predetermined repetition period in relation to the generation of each said V-sync signal and for producing a count-up signal upon counting said predetermined repetition period; phase comparing means for comparing the phase of said count-up signal with the phase of a V-sync signal and for producing a first level signal, representing the receipt of said standard signal, when the compared signals have the same phase, and a second level signal, representing the receipt of said non-standard signal, when the compared signals have different phase; second counter means for counting a predetermined time period, which is greater than said predetermined repetition period, in relation to the generation of said V-sync signal and for producing a time-up signal upon counting said predetermined time period; condition detecting means, which is connected receive said time-up signal and said V-sync signal, for detecting said absent condition when no V-sync signal appears before said time-up signal is produced, said condition detecting means producing a first level signal upon detection of said signal absent condition, and a second level signal when a v-sync signal appears before said time-up signal is produced; OR gate means for receiving signals from said phase comparing means and signals from said condition detecting means and for producing a first level signal when at least one of said phase comparing means and said condition detecting means is producing said first level signal; H-sync separation means for separating H-sync signals; and for controlling automatic frequency control means for controlling a frequency of a horizontal deflection in accordance with a frequency of said H-sync signals, said automatic frequency control means being arranged to operate under a low sensitive mode upon receipt of said first level signal from said OR gate means and to operate under a high sensitive mode upon receipt of a second level signal from said OR gate means.

Claim 17

A sync detection circuit for detecting a standard signal which is a signal having V-sync signals with a predetermined repetition period, a non-standard signal which is a signal having V-sync signals with a repetition period other than said predetermined repetition period, and a signal absent condition which occurs when the broadcasting is finished, or when a television receiver is switched to a non-broadcasting channel, said sync detection circuit comprising: V-sync separation means for separating V-sync signals; first counter means for counting said predetermined repetition period in relation to the generation of each said V-sync signal and for producing a count-up signal upon counting said predetermined repetition period; phase comparing means for comparing the phase of said count-up signal with the phase of a V-sync signal and for producing a first level signal, representing the receipt of said standard signal, when the compared signals have the same phase, and a second level signal, representing the receipt of said non-standard signal, when the compared signals have different phase; second counter means for counting a predetermined time period, which is greater than said predetermined repetition period, in relation to the generation of said V-sync signal and for producing a time-up signal upon counting said predetermined time period; condition detecting means, which is connected receive said time-up signal and said V-sync signal, for detecting said absent condition when no V-sync signal appears before said time-up signal is produced, said condition detecting means producing a first level signal upon detection of said signal absent condition, and a second level signal when a v-sync signal appears before said time-up signal is produced; OR gate means for receiving signals from said phase comparing means and signals from said condition detecting means and for producing a first level signal when at least one of said phase comparing means and said condition detecting means is producing said first level signal; H-sync separation means for separating H-sync signals; and for controlling automatic frequency control means for controlling a frequency of a horizontal deflection in accordance with a frequency of said H-sync signals, said automatic frequency control means being arranged to operate under a low sensitive mode upon receipt of said first level signal from said OR gate means and to operate under a high sensitive mode upon receipt of a second level signal from said OR gate means.