US4814712A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Test kit for a circuit breaker containing an electronic trip unit
Assignee: General Electric Co
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Filing: 1987-06-17
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Granted: 1989-03-21
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Expires: 2007-06-17
Abstract
Abstract A test kit for a digital and analog electronic circuit breaker determines the calibration and overcurrent response of the circuit breaker when connected within an electric power circuit. The test kit simulates an overcurrent condition and provides verification of the circuit breaker response without de-energizing the circuit breaker or interfering with the circuit breaker's protection functions. The test kit connects with the digital communications circuit within the digital circuit breaker to obtain status information concerning pick-up conditions, trip conditions and fault currents which are viewed on the test kit liquid crystal display. A ground fault suppression circuit is included within the test kit for single-phase current-injection without causing ground fault tripping. The test kit circuit further includes means for optionally tripping the circuit breaker upon completion of any of the tests.
Inventors
- 👤 Thomas D. Burton
- 👤 Indrajit Purkayastha
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 02:24
CPC Classifications
H; H02; H02H; H02H3/00; H02H3/02; H02H3/04; H02H3/044
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
155 words
A circuit breaker test unit comprising, in combination: a trip unit circuit within an electric circuit breaker connecting with three-phase conductors of a three-phase electric circuit and interacting with an operating mechanism for interrupting said electric circuit when circuit current exceeds preselected values; a test circuit within a test unit temporarily connected with said trip unit circuit; a power supply circuit within said test circuit connecting with said trip unit circuit and supplying power to said trip unit circuit when said trip unit is in a test condition; a microcomputer within said test circuit connected with said power supply circuit and a keyboard entry unit for inputting test parameters to said trip unit circuit; a digital communication circuit within said test circuit connected with said microcomputer; and display circuit means on said test unit connected with said microcomputer and displaying test data information received from said trip unit circuit in response to said test parameters.
Claim 2
Dependent Claim
155 words
A circuit breaker test unit comprising, in combination: a trip unit circuit within an electric circuit breaker connecting with three-phase conductors of a three-phase electric circuit and interacting with an operating mechanism for interrupting said electric circuit when circuit current exceeds preselected values; a test circuit within a test unit temporarily connected with said trip unit circuit; a power supply circuit within said test circuit connecting with said trip unit circuit and supplying power to said trip unit circuit when said trip unit is in a test condition; a microcomputer within said test circuit connected with said power supply circuit and a keyboard entry unit for inputting test parameters to said trip unit circuit; a digital communication circuit within said test circuit connected with said microcomputer; and display circuit means on said test unit connected with said microcomputer and displaying test data information received from said trip unit circuit in response to said test parameters.
Claim 3
Dependent Claim
32 words
The test unit of claim 1 including an overcurrent protection element within said test circuit connected in series with said power supply circuit to protect said power supply circuit from current surges.
Claim 4
Dependent Claim
18 words
The test unit circuit of claim 2 wherein said overcurrent protection element comprises a positive temperature coefficient element.
Claim 5
Dependent Claim
15 words
The test unit of claim 3 wherein said positive temperature coefficient element comprises a thermistor.
Claim 6
Dependent Claim
41 words
The test unit of claim 1 wherein said microcomputer includes a ground fault inhibit program whereby a ground fault current signal on one of said phase conductors is deterred from otherwise causing said trip unit circuit to interrupt said electric circuit.
Claim 7
Dependent Claim
65 words
The test unit circuit of claim 1 including a power bus conductor and a ground conductor within said power supply circuit, and further including a first test jack electrically connected across said power bus conductor and said ground conductor for providing external electrical access to said power supply circuit, said first test jack being connected with said digital communication circuit through a separate communications conductor.
Claim 8
Dependent Claim
34 words
The test unit of claim 6 further including a second test Jack electrically connected with a pair of separate conductors from a test circuit for providing a trip signal to said trip unit circuit.
Claim 9
Dependent Claim
28 words
The test unit of claim 7 wherein said test circuit includes a resistor and a capacitor connecting with said pair of separate conductors for providing said trip signal.
Claim 10
Dependent Claim
15 words
The test unit of claim 1 wherein said trip unit circuit includes a digital processor.
Claim 11
Dependent Claim
15 words
The test unit of claim 1 wherein said trip unit circuit includes an analog processor.
Claim 12
Independent Claim
114 words
A method of testing a circuit breaker trip unit comprising the steps of: providing a test unit containing a test unit circuit; temporarily connecting said test unit circuit to a trip unit circuit contained within a circuit breaker to institute a test condition; connecting a power supply circuit within said test unit circuit to said trip unit circuit for supplying operating power to said trip unit circuit during said test condition; displaying trip set points stored within said trip unit circuit on a display at said test unit; inactivating ground fault trip response to said trip unit circuit; and providing a ground fault inhibit command to a digital processor within said trip unit circuit.
Claim 13
Independent Claim
114 words
A method of testing a circuit breaker trip unit comprising the steps of: providing a test unit containing a test unit circuit; temporarily connecting said test unit circuit to a trip unit circuit contained within a circuit breaker to institute a test condition; connecting a power supply circuit within said test unit circuit to said trip unit circuit for supplying operating power to said trip unit circuit during said test condition; displaying trip set points stored within said trip unit circuit on a display at said test unit; inactivating ground fault trip response to said trip unit circuit; and providing a ground fault inhibit command to a digital processor within said trip unit circuit.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-03-20 | 1992-09-19 | 1993-03-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-03-20 | 1996-09-19 | 1997-03-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-03-20 | 2000-09-19 | 2001-03-21 | $7700.00 | Window Closed / Lapsed |