US4814646A
Expired / Lapsed
US
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Programmable logic array using emitter-coupled logic
Assignee: GlobalFoundries Inc
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Filing: 1985-03-22
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Granted: 1989-03-21
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Expires: 2005-03-22
Abstract
Abstract An ECL Programmable Logic Array (PLA) having ECL voltage level compatible input and output leads, thereby providing a high-speed PLA. A unique programming means is provided which allows the ECL PLA to be programmed using TTL-compatible programming voltage levels, such as are provided by common and inexpensive prior art TTL PLA programmers. In another embodiment higher speed is achieved by the design of each sense amplifier using emitter function logic such that the sense transistor and load functions a cascode amplifier. In another embodiment a lower power PLA device is achieved by utilizing a switched current source pull down means for pulling down the rows of the PLA array. In another embodiment low power and user convenience is achieved by allowing each pair of output terminals to share a predefined set of product terms. In another embodiment of this invention, each output terminal is capable of having its output polarity programmed, in order to provide either a desired product term, or the inverse of that product term.
Inventors
- 👤 Barry A. Hoberman
- 👤 William E. Moss
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 18:11
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/0008; H03K19/0016; H03K19/0175; H03K19/018; H03K19/01806; H03K19/02; H03K19/173; H03K19/177; H03K19/17704; H03K19/17708
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
123 words
A programmable logic array circuit comprising: ECL input buffer means for receiving ECL input signals and providing buffered signals; programmable ECL array means for combining said buffered input signals in a selectable manner and providing at least one first product term signal; logic means for performing a logic function on said at least one first product term signal and providing at least one second product term signal; ECL output buffer means for receiving said at least one second product term signal and providing an ECL output signal corresponding to each said at least one second product term signal; and programmable input buffer means for receiving programming input signals having signal levels other than ECL voltage levels, for programming said programmable logic array circuit.
Claim 2
Dependent Claim
123 words
A programmable logic array circuit comprising: ECL input buffer means for receiving ECL input signals and providing buffered signals; programmable ECL array means for combining said buffered input signals in a selectable manner and providing at least one first product term signal; logic means for performing a logic function on said at least one first product term signal and providing at least one second product term signal; ECL output buffer means for receiving said at least one second product term signal and providing an ECL output signal corresponding to each said at least one second product term signal; and programmable input buffer means for receiving programming input signals having signal levels other than ECL voltage levels, for programming said programmable logic array circuit.
Claim 3
Dependent Claim
17 words
A programmable logic array circuit as in claim 1 wherein said programming input signals have TTL levels.
Claim 4
Dependent Claim
147 words
A programmable logic array circuit comprising: programmable logic array means for combining a plurality of input signals in a selectable manner and providing at least one first product term signal; logic means for performing a logic function on said at least one first product term signal and providing at least one second product term signal; an output buffer; means for applying one of said at least one second product term signal to said output buffer comprising a transistor having a control terminal connected to receive a bias voltage, a first current handling terminal connected to receive said one second product term signal and a second current handling terminal connected to said output buffer; and a pull up means connected to a selected one of said current handling terminals to ensure said transistor never turns off in order to minimize voltage swing on said selected current handling terminals.
Claim 5
Dependent Claim
147 words
A programmable logic array circuit comprising: programmable logic array means for combining a plurality of input signals in a selectable manner and providing at least one first product term signal; logic means for performing a logic function on said at least one first product term signal and providing at least one second product term signal; an output buffer; means for applying one of said at least one second product term signal to said output buffer comprising a transistor having a control terminal connected to receive a bias voltage, a first current handling terminal connected to receive said one second product term signal and a second current handling terminal connected to said output buffer; and a pull up means connected to a selected one of said current handling terminals to ensure said transistor never turns off in order to minimize voltage swing on said selected current handling terminals.
Claim 6
Dependent Claim
111 words
A programmable logic array circuit comprising: programmable logic array means for combining a plurality of input signals in a selectable manner and providing at least one first product term signal; logic means for performing a logic function on said at least one first product term signal and providing at least one second product term signal; an output buffer; and means for applying one of said at least one second product term signal to said output buffer comprising a NPN transistor having a control terminal connected to receive a bias signal, having an emitter connected to receive said one second product term signal and having a collector connected to said output buffer.
Claim 7
Dependent Claim
111 words
A programmable logic array circuit comprising: programmable logic array means for combining a plurality of input signals in a selectable manner and providing at least one first product term signal; logic means for performing a logic function on said at least one first product term signal and providing at least one second product term signal; an output buffer; and means for applying one of said at least one second product term signal to said output buffer comprising a NPN transistor having a control terminal connected to receive a bias signal, having an emitter connected to receive said one second product term signal and having a collector connected to said output buffer.
Claim 8
Dependent Claim
115 words
A programmable logic array circuit comprising: programmable logic array means for combining a plurality of input signals in a selectable manner and providing at least one first product term signal; programmable logic means for performing a logic function on said at least one first product term signal and providing at least one second product term signal; an output buffer; and means for applying one of said at least one second product term signal to said output buffer comprising a transistor having a control terminal connected to receive a bias voltage, a first current handling terminal connected to receive said one second product term signal and a second current handling terminal connected to said output buffer.
Claim 9
Dependent Claim
115 words
A programmable logic array circuit comprising: programmable logic array means for combining a plurality of input signals in a selectable manner and providing at least one first product term signal; programmable logic means for performing a logic function on said at least one first product term signal and providing at least one second product term signal; an output buffer; and means for applying one of said at least one second product term signal to said output buffer comprising a transistor having a control terminal connected to receive a bias voltage, a first current handling terminal connected to receive said one second product term signal and a second current handling terminal connected to said output buffer.
Claim 10
Dependent Claim
136 words
A programmable logic array circuit comprising: programmable logic array means for combining a plurality of input signals in a selectable manner and providing at least on first product term signal; logic means for performing a logic function on said at least on first product term signal and providing at least one second product term signal; an output buffer; means for applying one of said at least one second product term signal to said output buffer comprising a transistor having a control terminal connected to receive a bias voltage, a first current handling terminal connected to receive said one second product term signal and a second current handling terminal connected to said output buffer; and pull up means connected to said first current handling terminal in order to minimize voltage swing on said selected current handling terminals.
Claim 11
Dependent Claim
136 words
A programmable logic array circuit comprising: programmable logic array means for combining a plurality of input signals in a selectable manner and providing at least on first product term signal; logic means for performing a logic function on said at least on first product term signal and providing at least one second product term signal; an output buffer; means for applying one of said at least one second product term signal to said output buffer comprising a transistor having a control terminal connected to receive a bias voltage, a first current handling terminal connected to receive said one second product term signal and a second current handling terminal connected to said output buffer; and pull up means connected to said first current handling terminal in order to minimize voltage swing on said selected current handling terminals.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-03-20 | 1992-09-19 | 1993-03-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-03-20 | 1996-09-19 | 1997-03-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-03-20 | 2000-09-19 | 2001-03-21 | $7700.00 | Window Closed / Lapsed |