US4814284A
Expired / Lapsed
US
⏱️ 0.0 years remaining
GaAs plannar diode and manufacturing method therefor
Assignee: Toshiba Corp
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Filing: 1987-10-22
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Granted: 1989-03-21
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Expires: 2007-10-22
Abstract
Abstract A GaAs planar diode includes an N type GaAs substrate having an N + GaAs layer on which an N - GaAs layer is formed. A first impurity layer of the N + type is formed on the N 31 GaAs layer. A second impurity layer of a p + type is formed on the first impurity layer, wherein a p-n junction is formed between the first and second impurity layers. A semi-insulation region, for encompassing a predetermined area of the p-n junction of the first and second impurity layers, is formed in the substrate. The depth of the semi-insulation region in the substrate is deeper than the total depth of the first and second impurity layers, so that the semi-insulation region serves as an element isolation region of the p-n junction of the first and second impurity layers.
Inventors
- 👤 Kazuhiko Inoue
- 👤 Yutaka Tomisawa
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 08:54
CPC Classifications
H; H10; H10D; H10D1/00; H10D1/01; H10D1/045; H10D1/60; H10D1/62; H10D1/64; H10W; H10W10/00; H10W10/01
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
212 words
A method for manufacturing a GaAs planar diode comprising the steps of: (a) forming a low-concentration first conductivity GaAs layer on a high-concentration first conductivity GaAs layer, to thereby provide a first conductivity substrate; (b) implanting a first kind of ion into a whole area of said low-concentration first conductivity GaAs layer, so that a first impurity layer of the high-concentration first conductivity type is formed on the whole area of said low-concentration first conductivity GaAs layer; (c) implanting a second kind of ion into a whole area of said first impurity layer, so that a second impurity layer of a high-concentration second conductivity type is formed on the whole area of said first impurity layer; (d) forming a mask for patterning a predetermined area of said second impurity layer, first impurity layer, and low-concentration first conductivity GaAs layer; (e) selectively-implanting predetermined atoms into said substrate except for the patterned predetermined area of said mask, so that a semi-insulation region serving as an element isolation region is formed around the patterned predetermined area of said mask, the depth of said semi-insulation region in said substrate having said first and second impurity layers being deeper than the total depth of said first ipurity layer, second impurity layer, and low-concentration first conductivity GaAs layer.
Claim 2
Independent Claim
212 words
A method for manufacturing a GaAs planar diode comprising the steps of: (a) forming a low-concentration first conductivity GaAs layer on a high-concentration first conductivity GaAs layer, to thereby provide a first conductivity substrate; (b) implanting a first kind of ion into a whole area of said low-concentration first conductivity GaAs layer, so that a first impurity layer of the high-concentration first conductivity type is formed on the whole area of said low-concentration first conductivity GaAs layer; (c) implanting a second kind of ion into a whole area of said first impurity layer, so that a second impurity layer of a high-concentration second conductivity type is formed on the whole area of said first impurity layer; (d) forming a mask for patterning a predetermined area of said second impurity layer, first impurity layer, and low-concentration first conductivity GaAs layer; (e) selectively-implanting predetermined atoms into said substrate except for the patterned predetermined area of said mask, so that a semi-insulation region serving as an element isolation region is formed around the patterned predetermined area of said mask, the depth of said semi-insulation region in said substrate having said first and second impurity layers being deeper than the total depth of said first ipurity layer, second impurity layer, and low-concentration first conductivity GaAs layer.
Claim 3
Independent Claim
28 words
A method according to claim, 1 wherein said semi-insulation region includes an element selected from the group consisting of boron (B), carbon (C), hydrogen (H), and oxygen (O).
Claim 4
Independent Claim
14 words
A method according to claim, 1 wherein said first impurity layer includes silicon (Si).
Claim 5
Independent Claim
14 words
A method according to claim, 1 wherein said second impurity layer includes zinc (Zn).
Claim 6
Independent Claim
223 words
A method for manufacturing a GaAs planar diode comprising the steps of: (a) forming a low-concentration first conductivity GaAs layer on a high-concentration first conductivity GaAs layer, to thereby provide a first conductivity substrate; (b) implanting a first kind of ion into a whole area of said low-concentration first conductivity GaAs layer, so that a first impurity layer of the high-concentration first conductivity type is formed on the whole area of said low-concentration first conductivity GaAs layer; (c) implanting a second kind of ion into a whole area of said first impurity layer, so that a second impurity layer of a high-concentration second conductivity type is formed on the whole area of said first impurity layer; (d) forming a first electrode on said second impurity layer, for patterning a predetermined area of said second impurity layer, first impurity layer, and low-concentration first conductivity GaAs layer, said first electrode ohmically contacting said second impurity layer; (e) selectively implanting predetermined atoms into said substrate except for the patterned predetermined area of said first electrode, so that a semi-insulation region serving as an element isolation region is formed around the patterned predetermined area of said first electrode, the depth of said semi-insulation region in said substrate being deeper than the total depth of said first impurity layer, second impurity layer, and low-concentration first conductivity GaAs layer.
Claim 7
Independent Claim
223 words
A method for manufacturing a GaAs planar diode comprising the steps of: (a) forming a low-concentration first conductivity GaAs layer on a high-concentration first conductivity GaAs layer, to thereby provide a first conductivity substrate; (b) implanting a first kind of ion into a whole area of said low-concentration first conductivity GaAs layer, so that a first impurity layer of the high-concentration first conductivity type is formed on the whole area of said low-concentration first conductivity GaAs layer; (c) implanting a second kind of ion into a whole area of said first impurity layer, so that a second impurity layer of a high-concentration second conductivity type is formed on the whole area of said first impurity layer; (d) forming a first electrode on said second impurity layer, for patterning a predetermined area of said second impurity layer, first impurity layer, and low-concentration first conductivity GaAs layer, said first electrode ohmically contacting said second impurity layer; (e) selectively implanting predetermined atoms into said substrate except for the patterned predetermined area of said first electrode, so that a semi-insulation region serving as an element isolation region is formed around the patterned predetermined area of said first electrode, the depth of said semi-insulation region in said substrate being deeper than the total depth of said first impurity layer, second impurity layer, and low-concentration first conductivity GaAs layer.
Claim 8
Independent Claim
28 words
A method according to clam 5, wherein said semi-insulation region includes an element selected from the group consisting of boron (B), carbon (C), hydrogen (H), and oxygen (O).
Claim 9
Independent Claim
28 words
A method according to clam 5, wherein said semi-insulation region includes an element selected from the group consisting of boron (B), carbon (C), hydrogen (H), and oxygen (O).
Claim 10
Dependent Claim
14 words
A method according to claim 5, wherein said second impurity layer includes zinc (Zn).
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 1992-03-20 | 1992-09-19 | 1993-03-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-03-20 | 1996-09-19 | 1997-03-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-03-20 | 2000-09-19 | 2001-03-21 | $7700.00 | Window Closed / Lapsed |