Triac desensitized with respect to re-striking risks on switching across a reactive load

Claim 1

A triac including a semiconductor structure having an upper face covered with a first main electrode and a gate electrode, and a lower face covered with a second main electrode, and further comprising: a type N central layer having an upper face side and lower face side; a first P type layer covering said central layer on said upper face side, a second P type layer covering said central layer on said lower face side, a first N type region formed in a part of the first P layer and being flush with the upper face in this part whereas the first P layer is flush with the rest of the upper face, the first N type region being pierced with emitter short circuit holes through which the first P layer rises and is flush with the upper surface, a second N type region formed in another part of the first P layer and being flush with the upper face in this other part, a third N type region formed in a part of the second P layer and flush with the lower face in this part whereas the second P layer is flush with the rest of the lower face, the third N type region being pierced with emitter short circuit holes through which the second P layer comes flush with the lower face, the first main electrode covering substantially the whole of the first N type region, including the short circuit holes of this first region, and covering a major flush part of the first P type layer, but not covering the first N type region and the first P type region in the immediate vicinity of the second N type region; the gate electrode covering substantially the whole of the second N type region as well as a flush part of the first P type layer, this part being spaced apart from the major flush part of the first P type layer and being connected to this major part by a flush portion of the first P type layer, this portion surrounding the second N type region and not being covered by an electrode; wherein, the gate electrode lies on top of three distinctive zones of superimposed semiconductor material; the first zone is partially in line with said gate electrode and comprises said first P type layer whose said flush part interfaces said gate electrode, said type N central layer which interfaces and lies below said first P type layer, and said second P type layer which interfaces and lies below said type N central layer and whose flush part interfaces said second main electrode; the second zone is partially in line with said gate electrode and comprises said second N type region whose flush part interfaces said gate electrode, said first P type layer which interfaces and lies below said second N type region, said type N central layer which interfaces and lies below said first P type layer, and said second P type layer which interfaces and lies below said type N central layer and whose flush part interfaces said second main electrode; the third zone is partially in line with said gate electrode and comprises said second N type region whose flush part interfaces said gate electrode, said first P type layer which interfaces and lies below said second N type region, said type N central layer which interfaces and lies below said first P type layer, said second P type layer which interfaces and lies below said type N central layer, and said third N type region which interfaces and lies below said second P type layer and whose flush part interfaces said second main electrode.