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US4812889A
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Semiconductor device FET with reduced energy level degeneration
Assignee: Toshiba Corp
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Filing: 1986-09-16
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Granted: 1989-03-14
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Expires: 2006-09-16
Abstract
Abstract A semiconductor device comprises a semiconductor substrate of a first conductivity type, a first impurity region of second conductivity which is formed in the substrate, a second impurity region of the second conductivity type which is formed in the substrate and spaced apart from the first semiconductor region, a channel region located between the first and second impurity regions, an insulation layer on the channel region, and a gate electrode on the insulation layer including conductive layer means for decreasing the temperature dependence of the semiconductor device, the layer means including a conductive layer and a semiconductive layer for reducing energy level degeneration.
Inventors
- 👤 Masakazu Kakumu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 05:32
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/80; H10D84/82; H10D84/83; H10D84/85; H10D84/858
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
130 words
A semiconductor device comprising: a semiconductor substrate of first conductivity; a first impurity region of second conductivity which is formed on the substrate; a second impurity region of the second conductivity which is formed in the substrate and spaced apart from said first impurity region; a channel region located between the first and second impurity regions; an insulation layer on the channel region; and a gate electrode formed on the insulation layer, said gate electrode including conductive layer means for decreasing the temperature dependence of the semiconductor device, said layer means including a semiconductive layer containing the impurity ions of the second conductivity of levels less than 10 16 /cm 3 which are insufficient to cause an energy level degeneration thereof and a conductive layer formed on the semiconductive layer.
Claim 2
Dependent Claim
130 words
A semiconductor device comprising: a semiconductor substrate of first conductivity; a first impurity region of second conductivity which is formed on the substrate; a second impurity region of the second conductivity which is formed in the substrate and spaced apart from said first impurity region; a channel region located between the first and second impurity regions; an insulation layer on the channel region; and a gate electrode formed on the insulation layer, said gate electrode including conductive layer means for decreasing the temperature dependence of the semiconductor device, said layer means including a semiconductive layer containing the impurity ions of the second conductivity of levels less than 10 16 /cm 3 which are insufficient to cause an energy level degeneration thereof and a conductive layer formed on the semiconductive layer.
Claim 3
Dependent Claim
14 words
A semiconductor device according to claim 1, wherein said semiconductive layer includes polycrystalline silicon.
Claim 4
Dependent Claim
15 words
A semiconductor device according to claim 1, wherein said conductive layer includes a metal silicide.
Claim 5
Dependent Claim
15 words
A semiconductor device according to claim 1, wherein said conductive layer includes a metal polycide.
Claim 6
Dependent Claim
24 words
A semiconductor device according to claim 2, wherein said polycrystalline silicon layer has an impurity concentration of less than 1×10 19 cm -3 .
Claim 7
Dependent Claim
40 words
A semiconductor device according to claim 3, wherein said metal silicide includes at least one member selected from the group consisting of molybdenum silicide, tungsten silicide, tantalum silicide, platinum silicide, titanium silicide , cobalt silicide, nickel silicide, and palladium silicide.
Claim 8
Dependent Claim
23 words
A semiconductor device according to claim 3, wherein the formation ratio of silicon to metal in said metal silicide is more than 2.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-03-13 | 1992-09-12 | 1993-03-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-03-13 | 1996-09-12 | 1997-03-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-03-13 | 2000-09-12 | 2001-03-14 | $7700.00 | Window Closed / Lapsed |